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                            ARM architecture family

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   "ARM architecture" redirects here. For the Australian architectural firm,
   see ARM Architecture (company).
   Link: mw-deduplicated-inline-style
   For the British semiconductor firm, see Arm Ltd.

   ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC
   Machines and originally Acorn RISC Machine) is a family of reduced
   instruction set computer (RISC) instruction set architectures for computer
   processors, configured for various environments. Arm Ltd. develops the
   architectures and licenses them to other companies, who design their own
   products that implement one or more of those architectures, including
   system on a chip (SoC) and system on module (SoM) designs, that
   incorporate different components such as memory, interfaces, and radios.
   It also designs cores that implement these instruction set architectures
   and licenses these designs to many companies that incorporate those core
   designs into their own products.

                                      ARM
   Arm logo 2017.svg
                * Sophie Wilson                  
   Designer     * Steve Furber                   
                * Acorn Computers/Arm Ltd.       
   Bits       32-bit, 64-bit                     
   Introduced 1985; 37 years ago                 
   Design     RISC                               
   Type       Register-Register                  
   Branching  Condition code, compare and branch 
   Open       Proprietary                        

   Link: mw-deduplicated-inline-style

                                 ARM 64/32-bit
   Introduced      2011; 11 years ago                                         
   Version         ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A,       
                   ARMv8.5-A, ARMv8.6-A, ARMv8-R, ARMv9                       
   Encoding        AArch64/A64 and AArch32/A32 use 32-bit instructions, T32   
                   (Thumb-2) uses mixed 16- and 32-bit instructions^[1]       
   Endianness      Bi (little as default)                                     
   Extensions      SVE, SVE2, SME, AES, SHA, TME; All mandatory: Thumb-2,     
                   Neon, VFPv4-D16, VFPv4; obsolete: Jazelle                  
   Registers       
   General purpose 31 × 64-bit integer registers^[1]                          
   Floating point  32 × 128-bit registers^[1] for scalar 32- and 64-bit FP or 
                   SIMD FP or integer; or cryptography                        

   Link: mw-deduplicated-inline-style

                              ARM 32-bit (Cortex)
   Version         ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R,      
                   ARMv7E-M, ARMv7-M, ARMv6-M                                 
   Encoding        32-bit, except Thumb-2 extensions use mixed 16- and 32-bit 
                   instructions.                                              
   Endianness      Bi (little as default)                                     
   Extensions      Thumb-2, Neon, Jazelle, AES, SHA, DSP, Saturated, FPv4-SP, 
                   FPv5, Helium                                               
   Registers       
   General purpose 15 × 32-bit integer registers, including R14 (link         
                   register), but not R15 (PC)                                
   Floating point  Up to 32 × 64-bit registers,^[2] SIMD/floating-point       
                   (optional)                                                 

   Link: mw-deduplicated-inline-style

                              ARM 32-bit (legacy)
   Version         ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2                         
   Encoding        32-bit, except Thumb extension uses mixed 16- and 32-bit   
                   instructions.                                              
   Endianness      Bi (little as default) in ARMv3 and above                  
   Extensions      Thumb, Jazelle                                             
   Registers       
   General purpose 15 × 32-bit integer registers, including R14 (link         
                   register), but not R15 (PC, 26-bit addressing in older)    
   Floating point  None                                                       

   There have been several generations of the ARM design. The original ARM1
   used a 32-bit internal structure but had a 26-bit address space that
   limited it to 64 MB of main memory. This limitation was removed in the
   ARMv3 series, which has a 32-bit address space, and several additional
   generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A
   architecture added support for a 64-bit address space and 64-bit
   arithmetic with its new 32-bit fixed-length instruction set.^[3] Arm Ltd.
   has also released a series of additional instruction sets for different
   rules; the "Thumb" extension adds both 32- and 16-bit instructions for
   improved code density, while Jazelle added instructions for directly
   handling Java bytecode. More recent changes include the addition of
   simultaneous multithreading (SMT) for improved performance or fault
   tolerance.^[4]

   Due to their low costs, minimal power consumption, and lower heat
   generation than their competitors, ARM processors are desirable for light,
   portable, battery-powered devices, including smartphones, laptops and
   tablet computers, and other embedded systems.^[5]^[6]^[7] However, ARM
   processors are also used for desktops and servers, including the world's
   fastest supercomputer.^[8] With over 200 billion ARM chips
   produced,^[9]^[10]^[11] as of 2021, ARM is the most widely used family of
   instruction set architectures (ISA) and the ISAs produced in the largest
   quantity.^[12]^[6]^[13]^[14]^[15] Currently, the widely used Cortex cores,
   older "classic" cores, and specialised SecurCore cores variants are
   available for each of these to include or exclude optional capabilities.

Contents

     * 1 History
          * 1.1 BBC Micro
          * 1.2 Acorn Business Computer
          * 1.3 Design concepts
          * 1.4 ARM1
          * 1.5 ARM2
          * 1.6 Advanced RISC Machines Ltd. – ARM6
          * 1.7 Early licensees
          * 1.8 Market share
     * 2 Licensing
          * 2.1 Core licence
          * 2.2 Built on ARM Cortex Technology licence
          * 2.3 Architectural licence
          * 2.4 ARM Flexible Access
     * 3 Cores
          * 3.1 Example applications of ARM cores
     * 4 32-bit architecture
          * 4.1 CPU modes
          * 4.2 Instruction set
               * 4.2.1 Arithmetic instructions
               * 4.2.2 Registers
               * 4.2.3 Conditional execution
               * 4.2.4 Other features
               * 4.2.5 Pipelines and other implementation issues
               * 4.2.6 Coprocessors
          * 4.3 Debugging
               * 4.3.1 Debug Access Port
          * 4.4 DSP enhancement instructions
          * 4.5 SIMD extensions for multimedia
          * 4.6 Jazelle
          * 4.7 Thumb
          * 4.8 Thumb-2
          * 4.9 Thumb Execution Environment (ThumbEE)
          * 4.10 Floating-point (VFP)
          * 4.11 Advanced SIMD (Neon)
          * 4.12 ARM Helium technology
          * 4.13 Security extensions
               * 4.13.1 TrustZone (for Cortex-A profile)
               * 4.13.2 TrustZone for ARMv8-M (for Cortex-M profile)
          * 4.14 No-execute page protection
          * 4.15 Large Physical Address Extension (LPAE)
          * 4.16 ARMv8-R and ARMv8-M
               * 4.16.1 ARMv8.1-M
     * 5 64/32-bit architecture
          * 5.1 ARMv8
               * 5.1.1 ARMv8-A
               * 5.1.2 ARMv8-R
          * 5.2 ARMv9
               * 5.2.1 ARMv9-A
     * 6 Arm SystemReady
     * 7 PSA Certified
     * 8 Operating system support
          * 8.1 32-bit operating systems
               * 8.1.1 Historical operating systems
               * 8.1.2 Embedded operating systems
               * 8.1.3 Mobile device operating systems
               * 8.1.4 Desktop/server operating systems
          * 8.2 64-bit operating systems
               * 8.2.1 Embedded operating systems
               * 8.2.2 Mobile device operating systems
               * 8.2.3 Desktop/server operating systems
          * 8.3 Porting to 32- or 64-bit ARM operating systems
     * 9 Notes
     * 10 See also
     * 11 References
          * 11.1 Citations
          * 11.2 Bibliography
     * 12 Further reading
     * 13 External links

HistoryEdit

  BBC MicroEdit

   Link: mw-deduplicated-inline-style
   Main article: BBC Micro

   Acorn Computers' first widely successful design was the BBC Micro,
   introduced in December 1981. This was a relatively conventional machine
   based on the MOS Technology 6502 CPU but ran at roughly double the
   performance of competing designs like the Apple II due to its use of
   faster dynamic random-access memory (DRAM). Typical DRAM of the era ran at
   about 2 MHz; Acorn arranged a deal with Hitachi for a supply of faster
   4 MHz parts.^[16]

   Machines of the era generally shared memory between the processor and the
   framebuffer, which allowed the processor to quickly update the contents of
   the screen without having to perform separate input/output (I/O). As the
   timing of the video display is exacting, the video hardware had to have
   priority access to that memory. Due to a quirk of the 6502's design, the
   CPU left the memory untouched for half of the time. Thus by running the
   CPU at 1 MHz, the video system could read data during those down times,
   taking up the total 2 MHz bandwidth of the RAM. In the BBC Micro, the use
   of 4 MHz RAM allowed the same technique to be used, but running at twice
   the speed. This allowed it to outperform any similar machine on the
   market.^[17]

  Acorn Business ComputerEdit

   Link: mw-deduplicated-inline-style
   Main article: Acorn Business Computer

   1981 was also the year that the IBM Personal Computer was introduced.
   Using the recently introduced Intel 8088, a 16-bit CPU compared to the
   6502's 8-bit design, it was able to offer higher overall performance. Its
   introduction changed the desktop computer market radically: what had been
   largely a hobby and gaming market emerging over the prior five years began
   to change to a must-have business tool where the earlier 8-bit designs
   simply could not compete. Even newer 32-bit designs were also coming to
   market, such as the Motorola 68000^[18] and National Semiconductor
   NS32016.^[19]

   Acorn began considering how to compete in this market and produced a new
   paper design named the Acorn Business Computer. They set themselves the
   goal of producing a machine with ten times the performance of the BBC
   Micro, but at the same price.^[20] This would outperform and underprice
   the PC. At the same time, the recent introduction of the Apple Lisa
   brought the graphical user interface (GUI) concept to a wider audience and
   suggested the future belonged to machines with a GUI.^[21] The Lisa,
   however, cost $9,995, as it was packed with support chips, large amounts
   of memory, and a hard disk drive, all very expensive then.^[22]

   The engineers then began studying all of the CPU designs available. Their
   conclusion about the existing 16-bit designs was that they were a lot more
   expensive and were still "a bit crap",^[23] offering only slightly higher
   performance than their BBC Micro design. They also almost always demanded
   a large number of support chips to operate even at that level, which drove
   up the cost of the computer as a whole. These systems would simply not hit
   the design goal.^[23] They also considered the new 32-bit designs, but
   these cost even more and had the same issues with support chips.^[24]
   According to Sophie Wilson, all the processors tested at that time
   performed about the same, with about a 4 Mbit/second bandwidth.^[25]^[a]

   Two key events led Acorn down the path to ARM. One was the publication of
   a series of reports from the University of California, Berkeley, which
   suggested that a simple chip design could nevertheless have extremely high
   performance, much higher than the latest 32-bit designs on the
   market.^[26] The second was a visit by Steve Furber and Sophie Wilson to
   the Western Design Center, a company run by Bill Mensch and his sister,
   which had become the logical successor to the MOS team and was offering
   new versions like the WDC 65C02. The Acorn team saw high school students
   producing chip layouts on Apple II machines, which suggested that anyone
   could do it.^[27]^[28] In contrast, a visit to another design firm working
   on modern 32-bit CPU revealed a team with over a dozen members which were
   already on revision H of their design and yet it still contained bugs.^[b]
   This cemented their late 1983 decision to begin their own CPU design, the
   Acorn RISC Machine.^[29]

  Design conceptsEdit

   The original Berkeley RISC designs were in some sense teaching systems,
   not designed specifically for outright performance. To the RISC's basic
   register-heavy and load/store concepts, ARM added a number of the
   well-received design notes of the 6502. Primary among them was the ability
   to quickly serve interrupts, which allowed the machines to offer
   reasonable input/output performance with no added external hardware. To
   offer interrupts with similar performance as the 6502, the ARM design
   limited its physical address space to 64 MB of total addressable space,
   requiring 26 bits of address. As instructions were 4 bytes (32 bits) long,
   and required to be aligned on 4-byte boundaries, the lower 2 bits of an
   instruction address were always zero. This meant the program counter (PC)
   only needed to be 24 bits, allowing it to be stored along with the eight
   bit processor flags in a single 32-bit register. That meant that on the
   reception of an interrupt, the entire machine state could be saved in a
   single operation, whereas had the PC been a full 32-bit value, it would
   require separate operations to store the PC and the status flags. This
   decision halved the interrupt overhead.^[30]

   Another change, and among the most important in terms of practical
   real-world performance, was the modification of the instruction set to
   take advantage of page mode DRAM. Recently introduced, page mode allowed
   subsequent accesses of memory to run twice as fast if they were roughly in
   the same location, or "page", in the DRAM chip. Berkeley's design did not
   consider page mode and treated all memory equally. The ARM design added
   special vector-like memory access instructions, the "S-cycles", that could
   be used to fill or save multiple registers in a single page using page
   mode. This doubled memory performance when they could be used, and was
   especially important for graphics performance.^[31]

   The Berkeley RISC designs used register windows to reduce the number of
   register saves and restores performed in procedure calls; the ARM design
   did not adopt this.

   Wilson developed the instruction set, writing a simulation of the
   processor in BBC BASIC that ran on a BBC Micro with a second 6502
   processor.^[32]^[33] This convinced Acorn engineers they were on the right
   track. Wilson approached Acorn's CEO, Hermann Hauser, and requested more
   resources. Hauser gave his approval and assembled a small team to design
   the actual processor based on Wilson's ISA.^[34] The official Acorn RISC
   Machine project started in October 1983.

  ARM1Edit

   [IMG] 
   Enlarge
   ARM1 2nd processor for the BBC Micro

   Acorn chose VLSI Technology as the "silicon partner", as they were a
   source of ROMs and custom chips for Acorn. Acorn provided the design and
   VLSI provided the layout and production. The first samples of ARM silicon
   worked properly when first received and tested on 26 April 1985.^[5] Known
   as ARM1, these versions ran at 6 MHz.^[35]

   The first ARM application was as a second processor for the BBC Micro,
   where it helped in developing simulation software to finish development of
   the support chips (VIDC, IOC, MEMC), and sped up the CAD software used in
   ARM2 development. Wilson subsequently rewrote BBC BASIC in ARM assembly
   language. The in-depth knowledge gained from designing the instruction set
   enabled the code to be very dense, making ARM BBC BASIC an extremely good
   test for any ARM emulator.

  ARM2Edit

   The result of the simulations on the ARM1 boards led to the late 1986
   introduction of the ARM2 design running at 8 MHz, and the early 1987
   speed-bumped version at 10 to 12 MHz.^[c] A significant change in the
   underlying architecture was the addition of a Booth multiplier, whereas
   formerly multiplication had to be carried out in software.^[37] Further, a
   new Fast Interrupt reQuest mode, FIQ for short, allowed registers 8
   through 14 to be replaced as part of the interrupt itself. This meant FIQ
   requests did not have to save out their registers, further speeding
   interrupts.^[38]

   The ARM2 was roughly seven times the performance of a typical 7 MHz
   68000-based system like the Commodore Amiga or Macintosh SE. It was twice
   as fast as an Intel 80386 running at 16 MHz, and about the same speed as a
   multi-processor VAX-11/784 superminicomputer. The only systems that beat
   it were the Sun SPARC and MIPS R2000 RISC-based workstations.^[39]
   Further, as the CPU was designed for high-speed I/O, it dispensed with
   many of the support chips seen in these machines; notably, it lacked any
   dedicated direct memory access (DMA) controller which was often found on
   workstations. The graphics system was also simplified based on the same
   set of underlying assumptions about memory and timing. The result was a
   dramatically simplified design, offering performance on par with expensive
   workstations but at a price point similar to contemporary desktops.^[39]

   The ARM2 featured a 32-bit data bus, 26-bit address space and 27 32-bit
   registers. The ARM2 had a transistor count of just 30,000,^[40] compared
   to Motorola's six-year-older 68000 model with around 68,000. Much of this
   simplicity came from the lack of microcode, which represents about
   one-quarter to one-third of the 68000's transistors, and the lack of (like
   most CPUs of the day) a cache. This simplicity enabled the ARM2 to have
   low power consumption, yet offer better performance than the Intel 80286.

   A successor, ARM3, was produced with a 4 KB cache, which further improved
   performance.^[41] The address bus was extended to 32 bits in the ARM6, but
   program code still had to lie within the first 64 MB of memory in 26-bit
   compatibility mode, due to the reserved bits for the status flags.^[42]

  Advanced RISC Machines Ltd. – ARM6Edit

   [IMG] 
   Enlarge
   Microprocessor-based system on a chip
   [IMG] 
   Enlarge
   Die of an ARM610 microprocessor

   In the late 1980s, Apple Computer and VLSI Technology started working with
   Acorn on newer versions of the ARM core. In 1990, Acorn spun off the
   design team into a new company named Advanced RISC Machines
   Ltd.,^[43]^[44]^[45] which became ARM Ltd. when its parent company, Arm
   Holdings plc, floated on the London Stock Exchange and NASDAQ in
   1998.^[46] The new Apple-ARM work would eventually evolve into the ARM6,
   first released in early 1992. Apple used the ARM6-based ARM610 as the
   basis for their Apple Newton PDA.

  Early licenseesEdit

   In 1994, Acorn used the ARM610 as the main central processing unit (CPU)
   in their RiscPC computers. DEC licensed the ARMv4 architecture and
   produced the StrongARM.^[47] At 233 MHz, this CPU drew only one watt
   (newer versions draw far less). This work was later passed to Intel as
   part of a lawsuit settlement, and Intel took the opportunity to supplement
   their i960 line with the StrongARM. Intel later developed its own high
   performance implementation named XScale, which it has since sold to
   Marvell. Transistor count of the ARM core remained essentially the same
   throughout these changes; ARM2 had 30,000 transistors,^[48] while ARM6
   grew only to 35,000.^[49]

  Market shareEdit

   In 2005, about 98% of all mobile phones sold used at least one ARM
   processor.^[50] In 2010, producers of chips based on ARM architectures
   reported shipments of 6.1 billion ARM-based processors, representing 95%
   of smartphones, 35% of digital televisions and set-top boxes and 10% of
   mobile computers. In 2011, the 32-bit ARM architecture was the most widely
   used architecture in mobile devices and the most popular 32-bit one in
   embedded systems.^[51] In 2013, 10 billion were produced^[52] and
   "ARM-based chips are found in nearly 60 percent of the world's mobile
   devices".^[53]

LicensingEdit

   Link: mw-deduplicated-inline-style
   See also: Arm Ltd. § Licensees
   [IMG] 
   Enlarge
   Die of a STM32F103VGT6 ARM Cortex-M3 microcontroller with 1 MB flash
   memory by STMicroelectronics

  Core licenceEdit

   Arm Ltd.'s primary business is selling IP cores, which licensees use to
   create microcontrollers (MCUs), CPUs, and systems-on-chips based on those
   cores. The original design manufacturer combines the ARM core with other
   parts to produce a complete device, typically one that can be built in
   existing semiconductor fabrication plants (fabs) at low cost and still
   deliver substantial performance. The most successful implementation has
   been the ARM7TDMI with hundreds of millions sold. Atmel has been a
   precursor design center in the ARM7TDMI-based embedded system.

   The ARM architectures used in smartphones, PDAs and other mobile devices
   range from ARMv5 to ARMv8-A.

   In 2009, some manufacturers introduced netbooks based on ARM architecture
   CPUs, in direct competition with netbooks based on Intel Atom.^[54]

   Arm Ltd. offers a variety of licensing terms, varying in cost and
   deliverables. Arm Ltd. provides to all licensees an integratable hardware
   description of the ARM core as well as complete software development
   toolset (compiler, debugger, software development kit) and the right to
   sell manufactured silicon containing the ARM CPU.

   SoC packages integrating ARM's core designs include Nvidia Tegra's first
   three generations, CSR plc's Quatro family, ST-Ericsson's Nova and
   NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP
   products, Samsung's Hummingbird and Exynos products, Apple's A4, A5, and
   A5X, and NXP's i.MX.

   Fabless licensees, who wish to integrate an ARM core into their own chip
   design, are usually only interested in acquiring a ready-to-manufacture
   verified semiconductor intellectual property core. For these customers,
   Arm Ltd. delivers a gate netlist description of the chosen ARM core, along
   with an abstracted simulation model and test programs to aid design
   integration and verification. More ambitious customers, including
   integrated device manufacturers (IDM) and foundry operators, choose to
   acquire the processor IP in synthesizable RTL (Verilog) form. With the
   synthesizable RTL, the customer has the ability to perform architectural
   level optimisations and extensions. This allows the designer to achieve
   exotic design goals not otherwise possible with an unmodified netlist
   (high clock speed, very low power consumption, instruction set extensions,
   etc.). While Arm Ltd. does not grant the licensee the right to resell the
   ARM architecture itself, licensees may freely sell manufactured products
   such as chip devices, evaluation boards and complete systems. Merchant
   foundries can be a special case; not only are they allowed to sell
   finished silicon containing ARM cores, they generally hold the right to
   re-manufacture ARM cores for other customers.

   Arm Ltd. prices its IP based on perceived value. Lower performing ARM
   cores typically have lower licence costs than higher performing cores. In
   implementation terms, a synthesisable core costs more than a hard macro
   (blackbox) core. Complicating price matters, a merchant foundry that holds
   an ARM licence, such as Samsung or Fujitsu, can offer fab customers
   reduced licensing costs. In exchange for acquiring the ARM core through
   the foundry's in-house design services, the customer can reduce or
   eliminate payment of ARM's upfront licence fee.

   Compared to dedicated semiconductor foundries (such as TSMC and UMC)
   without in-house design services, Fujitsu/Samsung charge two- to
   three-times more per manufactured wafer.^[citation needed] For low to mid
   volume applications, a design service foundry offers lower overall pricing
   (through subsidisation of the licence fee). For high volume mass-produced
   parts, the long term cost reduction achievable through lower wafer pricing
   reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making
   the dedicated foundry a better choice.

   Companies that have developed chips with cores designed by Arm Holdings
   include Amazon.com's Annapurna Labs subsidiary,^[55] Analog Devices,
   Apple, AppliedMicro (now: MACOM Technology Solutions^[56]), Atmel,
   Broadcom, Cavium, Cypress Semiconductor, Freescale Semiconductor (now NXP
   Semiconductors), Huawei, Intel,^[dubious – discuss] Maxim Integrated,
   Nvidia, NXP, Qualcomm, Renesas, Samsung Electronics, ST Microelectronics,
   Texas Instruments and Xilinx.

  Built on ARM Cortex Technology licenceEdit

   In February 2016, ARM announced the Built on ARM Cortex Technology
   licence, often shortened to Built on Cortex (BoC) licence. This licence
   allows companies to partner with ARM and make modifications to ARM Cortex
   designs. These design modifications will not be shared with other
   companies. These semi-custom core designs also have brand freedom, for
   example Kryo 280.

   Companies that are current licensees of Built on ARM Cortex Technology
   include Qualcomm.^[57]

  Architectural licenceEdit

   Companies can also obtain an ARM architectural licence for designing their
   own CPU cores using the ARM instruction sets. These cores must comply
   fully with the ARM architecture. Companies that have designed cores that
   implement an ARM architecture include Apple, AppliedMicro (now: Ampere
   Computing), Broadcom, Cavium (now: Marvell), Digital Equipment
   Corporation, Intel, Nvidia, Qualcomm, Samsung Electronics, Fujitsu, and
   NUVIA Inc.

  ARM Flexible AccessEdit

   On 16 July 2019, ARM announced ARM Flexible Access. ARM Flexible Access
   provides unlimited access to included ARM intellectual property (IP) for
   development. Per product licence fees are required once a customer reaches
   foundry tapeout or prototyping.^[58]^[59]

   75% of ARM's most recent IP over the last two years are included in ARM
   Flexible Access. As of October 2019:

     * CPUs: Cortex-A5, Cortex-A7, Cortex-A32, Cortex-A34, Cortex-A35,
       Cortex-A53, Cortex-R5, Cortex-R8, Cortex-R52, Cortex-M0, Cortex-M0+,
       Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33
     * GPUs: Mali-G52, Mali-G31. Includes Mali Driver Development Kits (DDK).
     * Interconnect: CoreLink NIC-400, CoreLink NIC-450, CoreLink CCI-400,
       CoreLink CCI-500, CoreLink CCI-550, ADB-400 AMBA, XHB-400 AXI-AHB
     * System Controllers: CoreLink GIC-400, CoreLink GIC-500, PL192 VIC,
       BP141 TrustZone Memory Wrapper, CoreLink TZC-400, CoreLink L2C-310,
       CoreLink MMU-500, BP140 Memory Interface
     * Security IP: CryptoCell-312, CryptoCell-712, TrustZone True Random
       Number Generator
     * Peripheral Controllers: PL011 UART, PL022 SPI, PL031 RTC
     * Debug & Trace: CoreSight SoC-400, CoreSight SDC-600, CoreSight
       STM-500, CoreSight System Trace Macrocell, CoreSight Trace Memory
       Controller
     * Design Kits: Corstone-101, Corstone-201
     * Physical IP: Artisan PIK for Cortex-M33 TSMC 22ULL including memory
       compilers, logic libraries, GPIOs and documentation
     * Tools & Materials: Socrates IP ToolingARM Design Studio, Virtual
       System Models
     * Support: Standard ARM Technical support, ARM online training,
       maintenance updates, credits towards onsite training and design
       reviews

CoresEdit

   Link: mw-deduplicated-inline-style
   Main article: List of ARM microarchitectures

Architecture Core      Cores                                   Profile         Refe-                          
             bit-width Arm Ltd.          Third-party                           rences                         
ARMv1        32        ARM1                                    Classic         ^[a 1]                         
ARMv2        32        ARM2, ARM250,     Amber, STORM Open     Classic         ^[a 1]                         
                       ARM3              Soft Core^[60]        
ARMv3        32        ARM6, ARM7                              Classic         ^[a 2]                         
                                         StrongARM, FA526, ZAP                 ^[a 2]                         
ARMv4        32        ARM8              Open Source Processor Classic         ^[61]                          
                                         Core                  
                       ARM7TDMI,                                                                              
ARMv4T       32        ARM9TDMI,                               Classic         ^[a 2]
                       SecurCore SC100   
ARMv5TE      32        ARM7EJ, ARM9E,    XScale, FA626TE,      Classic         
                       ARM10E            Feroceon, PJ1/Mohawk  
ARMv6        32        ARM11                                   Classic         
                       ARM Cortex-M0,                                          
ARMv6-M      32        ARM Cortex-M0+,                         Microcontroller
                       ARM Cortex-M1,    
                       SecurCore SC000   
ARMv7-M      32        ARM Cortex-M3,    Apple M7              Microcontroller 
                       SecurCore SC300   
ARMv7E-M     32        ARM Cortex-M4,                          Microcontroller 
                       ARM Cortex-M7     
                       ARM                                                                                    
ARMv8-M      32        Cortex-M23,^[62]                        Microcontroller ^[64]
                       ARM               
                       Cortex-M33^[63]   
                       ARM Cortex-R4,                                          
ARMv7-R      32        ARM Cortex-R5,                          Real-time
                       ARM Cortex-R7,    
                       ARM Cortex-R8     
ARMv8-R      32        ARM Cortex-R52                          Real-time       ^[65]^[66]^[67]                
             64        ARM Cortex-R82                          Real-time       
                       ARM Cortex-A5,                                          
                       ARM Cortex-A7,    Qualcomm              
                       ARM Cortex-A8,    Scorpion/Krait,       
ARMv7-A      32        ARM Cortex-A9,    PJ4/Sheeva, Apple     Application
                       ARM Cortex-A12,   Swift (A6, A6X)
                       ARM Cortex-A15,   
                       ARM Cortex-A17    
             32        ARM                                     Application     
                       Cortex-A32^[68]   
                                         X-Gene, Nvidia Denver                                                
                       ARM               1/2, Cavium ThunderX, 
                       Cortex-A35,^[69]  AMD K12, Apple        
                       ARM Cortex-A53,   Cyclone (A7)/Typhoon  
                       ARM               (A8, A8X)/Twister     
ARMv8-A      64/32     Cortex-A57,^[70]  (A9,                  Application     ^[73]^[74]^[75]^[76]^[77]^[78]
                       ARM               A9X)/Hurricane+Zephyr 
                       Cortex-A72,^[71]  (A10, A10X), Qualcomm 
                       ARM               Kryo, Samsung M1/M2   
                       Cortex-A73^[72]   ("Mongoose") /M3      
                                         ("Meerkat")           
             64        ARM                                     Application     
                       Cortex-A34^[79]   
ARMv8.1-A    64/32     TBA               Cavium ThunderX2      Application     ^[80]                          
                       ARM                                                                                    
                       Cortex-A55,^[81]                        
                       ARM               Nvidia Carmel,        
                       Cortex-A75,^[82]  Samsung M4            
             64/32     ARM               ("Cheetah"), Fujitsu  Application     ^[84]^[85]^[86]
                       Cortex-A76,^[83]  A64FX (ARMv8 SVE
                       ARM Cortex-A77,   512-bit)
                       ARM Cortex-A78,   
                       ARM Cortex-X1,    
                       ARM Neoverse N1   
                       ARM Cortex-A65,                                         
ARMv8.2-A              ARM Neoverse E1                         
                       with simultaneous                       
                       multithreading    
                       (SMT), ARM        
                       Cortex-A65AE^[87] Apple Monsoon+Mistral
             64        (also having e.g. (A11) (September      Application
                       ARMv8.4 Dot       2017)
                       Product; made for 
                       safety critical   
                       tasks such as     
                       advanced          
                       driver-assistance 
                       systems (ADAS))   
             64/32     TBA                                     Application     
                                         Apple Vortex+Tempest                  
ARMv8.3-A    64        TBA               (A12, A12X, A12Z),    Application
                                         Marvell ThunderX3     
                                         (v8.3+)^[88]          
             64/32     TBA                                     Application     
                                         Apple                                 
                                         Lightning+Thunder     
ARMv8.4-A                                (A13), Apple          
             64        TBA               Firestorm+Icestorm    Application
                                         (A14), Apple          
                                         Firestorm+Icestorm    
                                         (M1)                  
             64/32     TBA                                     Application     
ARMv8.5-A                                Apple                                 
             64        TBA               Avalanche+Blizzard    Application
                                         (A15)                 
ARMv8.6-A    64        TBA                                     Application     
ARMv8.7-A    64        TBA                                     Application     ^[89]                          
                       ARM Cortex-A510,                                                                       
ARMv9-A      64        ARM Cortex-A710,                        Application     ^[90]^[91]
                       ARM Cortex-X2,    
                       ARM Neoverse N2   

    1. ^ ^a ^b Although most datapaths and CPU registers in the early ARM
       processors were 32-bit, addressable memory was limited to 26 bits;
       with upper bits, then, used for status flags in the program counter
       register.
    2. ^ ^a ^b ^c ARMv3 included a compatibility mode to support the 26-bit
       addresses of earlier versions of the architecture. This compatibility
       mode optional in ARMv4, and removed entirely in ARMv5.

   Arm Holdings provides a list of vendors who implement ARM cores in their
   design (application specific standard products (ASSP), microprocessor and
   microcontrollers).^[92]

  Example applications of ARM coresEdit

   [IMG] 
   Enlarge
   Tronsmart MK908, a Rockchip-based quad-core Android "mini PC", with a
   microSD card next to it for a size comparison
   Link: mw-deduplicated-inline-style
   Main article: List of applications of ARM cores

   ARM cores are used in a number of products, particularly PDAs and
   smartphones. Some computing examples are Microsoft's first generation
   Surface, Surface 2 and Pocket PC devices (following 2002), Apple's iPads
   and Asus's Eee Pad Transformer tablet computers, and several Chromebook
   laptops. Others include Apple's iPhone smartphones and iPod portable media
   players, Canon PowerShot digital cameras, Nintendo Switch hybrid, the Wii
   security processor and 3DS handheld game consoles, and TomTom turn-by-turn
   navigation systems.

   In 2005, Arm Holdings took part in the development of Manchester
   University's computer SpiNNaker, which used ARM cores to simulate the
   human brain.^[93]

   ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone,
   PandaBoard and other single-board computers, because they are very small,
   inexpensive and consume very little power.

32-bit architectureEdit

   [IMG] 
   Enlarge
   An ARMv7 was used to power older versions of the popular Raspberry Pi
   single-board computers like this Raspberry Pi 2 from 2015.
   [IMG] 
   Enlarge
   An ARMv7 is also used to power the CuBox family of single-board computers.
   Link: mw-deduplicated-inline-style
   See also: Comparison of ARMv7-A cores

   The 32-bit ARM architecture (ARM32), such as ARMv7-A (implementing
   AArch32; see section on ARMv8-A for more on it), was the most widely used
   architecture in mobile devices as of 2011.^[51]

   Since 1995, various versions of the ARM Architecture Reference Manual (see
   § External links) have been the primary source of documentation on the ARM
   processor architecture and instruction set, distinguishing interfaces that
   all ARM processors are required to support (such as instruction semantics)
   from implementation details that may vary. The architecture has evolved
   over time, and version seven of the architecture, ARMv7, defines three
   architecture "profiles":

     * A-profile, the "Application" profile, implemented by 32-bit cores in
       the Cortex-A series and by some non-ARM cores
     * R-profile, the "Real-time" profile, implemented by cores in the
       Cortex-R series
     * M-profile, the "Microcontroller" profile, implemented by most cores in
       the Cortex-M series

   Although the architecture profiles were first defined for ARMv7, ARM
   subsequently defined the ARMv6-M architecture (used by the Cortex
   M0/M0+/M1) as a subset of the ARMv7-M profile with fewer instructions.

  CPU modesEdit

   Except in the M-profile, the 32-bit ARM architecture specifies several CPU
   modes, depending on the implemented architecture features. At any moment
   in time, the CPU can be in only one mode, but it can switch modes due to
   external events (interrupts) or programmatically.^[94]

     * User mode: The only non-privileged mode.
     * FIQ mode: A privileged mode that is entered whenever the processor
       accepts a fast interrupt request.
     * IRQ mode: A privileged mode that is entered whenever the processor
       accepts an interrupt.
     * Supervisor (svc) mode: A privileged mode entered whenever the CPU is
       reset or when an SVC instruction is executed.
     * Abort mode: A privileged mode that is entered whenever a prefetch
       abort or data abort exception occurs.
     * Undefined mode: A privileged mode that is entered whenever an
       undefined instruction exception occurs.
     * System mode (ARMv4 and above): The only privileged mode that is not
       entered by an exception. It can only be entered by executing an
       instruction that explicitly writes to the mode bits of the Current
       Program Status Register (CPSR) from another privileged mode (not from
       user mode).
     * Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3): A
       monitor mode is introduced to support TrustZone extension in ARM
       cores.
     * Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2): A hypervisor
       mode that supports Popek and Goldberg virtualization requirements for
       the non-secure operation of the CPU.^[95]^[96]
     * Thread mode (ARMv6-M, ARMv7-M, ARMv8-M): A mode which can be specified
       as either privileged or unprivileged. Whether the Main Stack Pointer
       (MSP) or Process Stack Pointer (PSP) is used can also be specified in
       CONTROL register with privileged access. This mode is designed for
       user tasks in RTOS environment but it's typically used in bare-metal
       for super-loop.
     * Handler mode (ARMv6-M, ARMv7-M, ARMv8-M): A mode dedicated for
       exception handling (except the RESET which are handled in Thread
       mode). Handler mode always uses MSP and works in privileged level.

  Instruction setEdit

   The original (and subsequent) ARM implementation was hardwired without
   microcode, like the much simpler 8-bit 6502 processor used in prior Acorn
   microcomputers.

   The 32-bit ARM architecture (and the 64-bit architecture for the most
   part) includes the following RISC features:

     * Load/store architecture.
     * No support for unaligned memory accesses in the original version of
       the architecture. ARMv6 and later, except some microcontroller
       versions, support unaligned accesses for half-word and single-word
       load/store instructions with some limitations, such as no guaranteed
       atomicity.^[97]^[98]
     * Uniform 16 × 32-bit register file (including the program counter,
       stack pointer and the link register).
     * Fixed instruction width of 32 bits to ease decoding and pipelining, at
       the cost of decreased code density. Later, the Thumb instruction set
       added 16-bit instructions and increased code density.
     * Mostly single clock-cycle execution.

   To compensate for the simpler design, compared with processors like the
   Intel 80286 and Motorola 68020, some additional design features were used:

     * Conditional execution of most instructions reduces branch overhead and
       compensates for the lack of a branch predictor in early chips.
     * Arithmetic instructions alter condition codes only when desired.
     * 32-bit barrel shifter can be used without performance penalty with
       most arithmetic instructions and address calculations.
     * Has powerful indexed addressing modes.
     * A link register supports fast leaf function calls.
     * A simple, but fast, 2-priority-level interrupt subsystem has switched
       register banks.

    Arithmetic instructionsEdit

   ARM includes integer arithmetic operations for add, subtract, and
   multiply; some versions of the architecture also support divide
   operations.

   ARM supports 32-bit × 32-bit multiplies with either a 32-bit result or
   64-bit result, though Cortex-M0 / M0+ / M1 cores don't support 64-bit
   results.^[99] Some ARM cores also support 16-bit × 16-bit and 32-bit ×
   16-bit multiplies.

   The divide instructions are only included in the following ARM
   architectures:

     * ARMv7-M and ARMv7E-M architectures always include divide
       instructions.^[100]
     * ARMv7-R architecture always includes divide instructions in the Thumb
       instruction set, but optionally in its 32-bit instruction set.^[101]
     * ARMv7-A architecture optionally includes the divide instructions. The
       instructions might not be implemented, or implemented only in the
       Thumb instruction set, or implemented in both the Thumb and ARM
       instruction sets, or implemented if the Virtualization Extensions are
       included.^[101]

    RegistersEdit

                           Registers across CPU modes
   usr sys svc      abt      und      irq      fiq      
   R0  
   R1  
   R2  
   R3  
   R4  
   R5  
   R6  
   R7  
                       R8                       R8_fiq  
                       R9                       R9_fiq  
                       R10                     R10_fiq  
                       R11                     R11_fiq  
                       R12                     R12_fiq  
     R13   R13_svc  R13_abt  R13_und  R13_irq  R13_fiq  
     R14   R14_svc  R14_abt  R14_und  R14_irq  R14_fiq  
   R15 
   CPSR
           SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq 

   Registers R0 through R7 are the same across all CPU modes; they are never
   banked.

   Registers R8 through R12 are the same across all CPU modes except FIQ
   mode. FIQ mode has its own distinct R8 through R12 registers.

   R13 and R14 are banked across all privileged CPU modes except system mode.
   That is, each mode that can be entered because of an exception has its own
   R13 and R14. These registers generally contain the stack pointer and the
   return address from function calls, respectively.

   Aliases:

     * R13 is also referred to as SP, the Stack Pointer.
     * R14 is also referred to as LR, the Link Register.
     * R15 is also referred to as PC, the Program Counter.

   The Current Program Status Register (CPSR) has the following
   32 bits.^[102]

     * M (bits 0–4) is the processor mode bits.
     * T (bit 5) is the Thumb state bit.
     * F (bit 6) is the FIQ disable bit.
     * I (bit 7) is the IRQ disable bit.
     * A (bit 8) is the imprecise data abort disable bit.
     * E (bit 9) is the data endianness bit.
     * IT (bits 10–15 and 25–26) is the if-then state bits.
     * GE (bits 16–19) is the greater-than-or-equal-to bits.
     * DNM (bits 20–23) is the do not modify bits.
     * J (bit 24) is the Java state bit.
     * Q (bit 27) is the sticky overflow bit.
     * V (bit 28) is the overflow bit.
     * C (bit 29) is the carry/borrow/extend bit.
     * Z (bit 30) is the zero bit.
     * N (bit 31) is the negative/less than bit.

    Conditional executionEdit

   Almost every ARM instruction has a conditional execution feature called
   predication, which is implemented with a 4-bit condition code selector
   (the predicate). To allow for unconditional execution, one of the four-bit
   codes causes the instruction to be always executed. Most other CPU
   architectures only have condition codes on branch instructions.^[103]

   Though the predicate takes up four of the 32 bits in an instruction code,
   and thus cuts down significantly on the encoding bits available for
   displacements in memory access instructions, it avoids branch instructions
   when generating code for small if statements. Apart from eliminating the
   branch instructions themselves, this preserves the fetch/decode/execute
   pipeline at the cost of only one cycle per skipped instruction.

   An algorithm that provides a good example of conditional execution is the
   subtraction-based Euclidean algorithm for computing the greatest common
   divisor. In the C programming language, the algorithm can be written as:

 int gcd(int a, int b) {
   while (a != b)  // We enter the loop when a<b or a>b, but not when a==b
     if (a > b)   // When a>b we do this
       a -= b;
     else         // When a<b we do that (no if(a<b) needed since a!=b is checked in while condition)
       b -= a;
   return a;
 }

   The same algorithm can be rewritten in a way closer to target ARM
   instructions as:

 loop:
     // Compare a and b
     GT = a > b;
     LT = a < b;
     NE = a != b;

     // Perform operations based on flag results
     if(GT) a -= b;    // Subtract *only* if greater-than
     if(LT) b -= a;    // Subtract *only* if less-than
     if(NE) goto loop; // Loop *only* if compared values were not equal
     return a;

   and coded in assembly language as:

 ; assign a to register r0, b to r1
 loop:   CMP    r0, r1       ; set condition "NE" if (a != b),
                             ;               "GT" if (a > b),
                             ;            or "LT" if (a < b)
         SUBGT  r0, r0, r1   ; if "GT" (Greater Than), then a = a-b
         SUBLT  r1, r1, r0   ; if "LT" (Less Than), then b = b-a
         BNE  loop           ; if "NE" (Not Equal), then loop
         B    lr             ; return

   which avoids the branches around the then and else clauses. If r0 and r1
   are equal then neither of the SUB instructions will be executed,
   eliminating the need for a conditional branch to implement the while check
   at the top of the loop, for example had SUBLE (less than or equal) been
   used.

   One of the ways that Thumb code provides a more dense encoding is to
   remove the four-bit selector from non-branch instructions.

    Other featuresEdit

   Another feature of the instruction set is the ability to fold shifts and
   rotates into the data processing (arithmetic, logical, and
   register-register move) instructions, so that, for example, the statement
   in C language:

 a += (j << 2);

   could be rendered as a one-word, one-cycle instruction:^[104]

 ADD  Ra, Ra, Rj, LSL #2

   This results in the typical ARM program being denser than expected with
   fewer memory accesses; thus the pipeline is used more efficiently.

   The ARM processor also has features rarely seen in other RISC
   architectures, such as PC-relative addressing (indeed, on the 32-bit^[1]
   ARM the PC is one of its 16 registers) and pre- and post-increment
   addressing modes.

   The ARM instruction set has increased over time. Some early ARM processors
   (before ARM7TDMI), for example, have no instruction to store a two-byte
   quantity.

    Pipelines and other implementation issuesEdit

   The ARM7 and earlier implementations have a three-stage pipeline; the
   stages being fetch, decode and execute. Higher-performance designs, such
   as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages.
   Additional implementation changes for higher performance include a faster
   adder and more extensive branch prediction logic. The difference between
   the ARM7DI and ARM7DMI cores, for example, was an improved multiplier;
   hence the added "M".

    CoprocessorsEdit

   The ARM architecture (pre-ARMv8) provides a non-intrusive way of extending
   the instruction set using "coprocessors" that can be addressed using MCR,
   MRC, MRRC, MCRR and similar instructions. The coprocessor space is divided
   logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15
   (cp15) being reserved for some typical control functions like managing the
   caches and MMU operation on processors that have one.

   In ARM-based machines, peripheral devices are usually attached to the
   processor by mapping their physical registers into ARM memory space, into
   the coprocessor space, or by connecting to another device (a bus) that in
   turn attaches to the processor. Coprocessor accesses have lower latency,
   so some peripherals—for example, an XScale interrupt controller—are
   accessible in both ways: through memory and through coprocessors.

   In other cases, chip designers only integrate hardware using the
   coprocessor mechanism. For example, an image processing engine might be a
   small ARM7TDMI core combined with a coprocessor that has specialised
   operations to support a specific set of HDTV transcoding primitives.

  DebuggingEdit

   This section needs additional citations for verification. Please help      
   improve this article by adding citations to reliable sources. Unsourced    
   material may be challenged and removed. (March 2011) (Learn how and when   
   to remove this template message)                                           

   All modern ARM processors include hardware debugging facilities, allowing
   software debuggers to perform operations such as halting, stepping, and
   breakpointing of code starting from reset. These facilities are built
   using JTAG support, though some newer cores optionally support ARM's own
   two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug
   support, and the "I" represented presence of an "EmbeddedICE" debug
   module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de
   facto debug standard, though not architecturally guaranteed.

   The ARMv7 architecture defines basic debug facilities at an architectural
   level. These include breakpoints, watchpoints and instruction execution in
   a "Debug Mode"; similar facilities were also available with EmbeddedICE.
   Both "halt mode" and "monitor" mode debugging are supported. The actual
   transport mechanism used to access the debug facilities is not
   architecturally specified, but implementations generally include JTAG
   support.

   There is a separate ARM "CoreSight" debug architecture, which is not
   architecturally required by ARMv7 processors.

    Debug Access PortEdit

   The Debug Access Port (DAP) is an implementation of an ARM Debug
   Interface.^[105] There are two different supported implementations, the
   Serial Wire JTAG Debug Port (SWJ-DP) and the Serial Wire Debug Port
   (SW-DP).^[106] CMSIS-DAP is a standard interface that describes how
   various debugging software on a host PC can communicate over USB to
   firmware running on a hardware debugger, which in turn talks over SWD or
   JTAG to a CoreSight-enabled ARM Cortex CPU.^[107]^[108]^[109]^[110]

  DSP enhancement instructionsEdit

   To improve the ARM architecture for digital signal processing and
   multimedia applications, DSP instructions were added to the set.^[111]
   These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ
   architectures. E-variants also imply T, D, M, and I.

   The new instructions are common in digital signal processor (DSP)
   architectures. They include variations on signed multiply–accumulate,
   saturated add and subtract, and count leading zeros.

  SIMD extensions for multimediaEdit

   Introduced in the ARMv6 architecture, this was a precursor to Advanced
   SIMD, also named Neon.^[112]

  JazelleEdit

   Link: mw-deduplicated-inline-style
   Main article: Jazelle

   Jazelle DBX (Direct Bytecode eXecution) is a technique that allows Java
   bytecode to be executed directly in the ARM architecture as a third
   execution state (and instruction set) alongside the existing ARM and
   Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ
   architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this
   state is required starting in ARMv6 (except for the ARMv7-M profile),
   though newer cores only include a trivial implementation that provides no
   hardware acceleration.

  ThumbEdit

   To improve compiled code density, processors since the ARM7TDMI (released
   in 1994^[113]) have featured the Thumb instruction set, which have their
   own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this
   state, the processor executes the Thumb instruction set, a compact 16-bit
   encoding for a subset of the ARM instruction set.^[114] Most of the Thumb
   instructions are directly mapped to normal ARM instructions. The space
   saving comes from making some of the instruction operands implicit and
   limiting the number of possibilities compared to the ARM instructions
   executed in the ARM instruction set state.

   In Thumb, the 16-bit opcodes have less functionality. For example, only
   branches can be conditional, and many opcodes are restricted to accessing
   only half of all of the CPU's general-purpose registers. The shorter
   opcodes give improved code density overall, even though some operations
   require extra instructions. In situations where the memory port or bus
   width is constrained to less than 32 bits, the shorter Thumb opcodes allow
   increased performance compared with 32-bit ARM code, as less program code
   may need to be loaded into the processor over the constrained memory
   bandwidth.

   Unlike processor architectures with variable length (16- or 32-bit)
   instructions, such as the Cray-1 and Hitachi SuperH, the ARM and Thumb
   instruction sets exist independently of each other. Embedded hardware,
   such as the Game Boy Advance, typically have a small amount of RAM
   accessible with a full 32-bit datapath; the majority is accessed via a
   16-bit or narrower secondary datapath. In this situation, it usually makes
   sense to compile Thumb code and hand-optimise a few of the most
   CPU-intensive sections using full 32-bit ARM instructions, placing these
   wider instructions into the 32-bit bus accessible memory.

   The first processor with a Thumb instruction decoder was the ARM7TDMI. All
   ARM9 and later families, including XScale, have included a Thumb
   instruction decoder. It includes instructions adopted from the Hitachi
   SuperH (1992), which was licensed by ARM.^[115] ARM's smallest processor
   families (Cortex M0 and M1) implement only the 16-bit Thumb instruction
   set for maximum performance in lowest cost applications.

  Thumb-2Edit

   Thumb-2 technology was introduced in the ARM1156 core, announced in 2003.
   Thumb-2 extends the limited 16-bit instruction set of Thumb with
   additional 32-bit instructions to give the instruction set more breadth,
   thus producing a variable-length instruction set. A stated aim for Thumb-2
   was to achieve code density similar to Thumb with performance similar to
   the ARM instruction set on 32-bit memory.

   Thumb-2 extends the Thumb instruction set with bit-field manipulation,
   table branches and conditional execution. At the same time, the ARM
   instruction set was extended to maintain equivalent functionality in both
   instruction sets. A new "Unified Assembly Language" (UAL) supports
   generation of either Thumb or ARM instructions from the same source code;
   versions of Thumb seen on ARMv7 processors are essentially as capable as
   ARM code (including the ability to write interrupt handlers). This
   requires a bit of care, and use of a new "IT" (if-then) instruction, which
   permits up to four successive instructions to execute based on a tested
   condition, or on its inverse. When compiling into ARM code, this is
   ignored, but when compiling into Thumb it generates an actual instruction.
   For example:

 ; if (r0 == r1)
 CMP r0, r1
 ITE EQ        ; ARM: no code ... Thumb: IT instruction
 ; then r0 = r2;
 MOVEQ r0, r2  ; ARM: conditional; Thumb: condition via ITE 'T' (then)
 ; else r0 = r3;
 MOVNE r0, r3  ; ARM: conditional; Thumb: condition via ITE 'E' (else)
 ; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE".

   All ARMv7 chips support the Thumb instruction set. All chips in the
   Cortex-A series, Cortex-R series, and ARM11 series support both "ARM
   instruction set state" and "Thumb instruction set state", while chips in
   the Cortex-M series support only the Thumb instruction
   set.^[116]^[117]^[118]

  Thumb Execution Environment (ThumbEE)Edit

   ThumbEE (erroneously called Thumb-2EE in some ARM documentation), which
   was marketed as Jazelle RCT^[119] (Runtime Compilation Target), was
   announced in 2005 and deprecated in 2011. It first appeared in the
   Cortex-A8 processor. ThumbEE is a fourth instruction set state, making
   small changes to the Thumb-2 extended instruction set. These changes make
   the instruction set particularly suited to code generated at runtime (e.g.
   by JIT compilation) in managed Execution Environments. ThumbEE is a target
   for languages such as Java, C#, Perl, and Python, and allows JIT compilers
   to output smaller compiled code without impacting performance.^[citation
   needed]

   New features provided by ThumbEE include automatic null pointer checks on
   every load and store instruction, an instruction to perform an array
   bounds check, and special instructions that call a handler. In addition,
   because it utilises Thumb-2 technology, ThumbEE provides access to
   registers r8–r15 (where the Jazelle/DBX Java VM state is held).^[120]
   Handlers are small sections of frequently called code, commonly used to
   implement high level languages, such as allocating memory for a new
   object. These changes come from repurposing a handful of opcodes, and
   knowing the core is in the new ThumbEE state.

   On 23 November 2011, Arm Holdings deprecated any use of the ThumbEE
   instruction set,^[121] and ARMv8 removes support for ThumbEE.

  Floating-point (VFP)Edit

   VFP (Vector Floating Point) technology is a floating-point unit (FPU)
   coprocessor extension to the ARM architecture^[122] (implemented
   differently in ARMv8 – coprocessors not defined there). It provides
   low-cost single-precision and double-precision floating-point computation
   fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary
   Floating-Point Arithmetic. VFP provides floating-point computation
   suitable for a wide spectrum of applications such as PDAs, smartphones,
   voice compression and decompression, three-dimensional graphics and
   digital audio, printers, set-top boxes, and automotive applications. The
   VFP architecture was intended to support execution of short "vector mode"
   instructions but these operated on each vector element sequentially and
   thus did not offer the performance of true single instruction, multiple
   data (SIMD) vector parallelism. This vector mode was therefore removed
   shortly after its introduction,^[123] to be replaced with the much more
   powerful Advanced SIMD, also named Neon.

   Some devices such as the ARM Cortex-A8 have a cut-down VFPLite module
   instead of a full VFP module, and require roughly ten times more clock
   cycles per float operation.^[124] Pre-ARMv8 architecture implemented
   floating-point/SIMD with the coprocessor interface. Other floating-point
   and/or SIMD units found in ARM-based processors using the coprocessor
   interface include FPA, FPE, iwMMXt, some of which were implemented in
   software by trapping but could have been implemented in hardware. They
   provide some of the same functionality as VFP but are not
   opcode-compatible with it. FPA10 also provides extended precision, but
   implements correct rounding (required by IEEE 754) only in single
   precision.^[125]

   VFPv1
           Obsolete

   VFPv2
           An optional extension to the ARM instruction set in the ARMv5TE,
           ARMv5TEJ and ARMv6 architectures. VFPv2 has 16 64-bit FPU
           registers.

   VFPv3 or VFPv3-D32
           Implemented on most Cortex-A8 and A9 ARMv7 processors. It is
           backwards compatible with VFPv2, except that it cannot trap
           floating-point exceptions. VFPv3 has 32 64-bit FPU registers as
           standard, adds VCVT instructions to convert between scalar, float
           and double, adds immediate mode to VMOV such that constants can be
           loaded into FPU registers.

   VFPv3-D16
           As above, but with only 16 64-bit FPU registers. Implemented on
           Cortex-R4 and R5 processors and the Tegra 2 (Cortex-A9).

   VFPv3-F16
           Uncommon; it supports IEEE754-2008 half-precision (16-bit)
           floating point as a storage format.

   VFPv4 or VFPv4-D32
           Implemented on Cortex-A12 and A15 ARMv7 processors, Cortex-A7
           optionally has VFPv4-D32 in the case of an FPU with Neon.^[126]
           VFPv4 has 32 64-bit FPU registers as standard, adds both
           half-precision support as a storage format and fused
           multiply-accumulate instructions to the features of VFPv3.

   VFPv4-D16
           As above, but it has only 16 64-bit FPU registers. Implemented on
           Cortex-A5 and A7 processors in the case of an FPU without
           Neon.^[126]

   VFPv5-D16-M
           Implemented on Cortex-M7 when single and double-precision
           floating-point core option exists.

   In Debian Linux, and derivatives such as Ubuntu and Linux Mint, armhf (ARM
   hard float) refers to the ARMv7 architecture including the additional
   VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software
   packages and cross-compiler tools use the armhf vs. arm/armel suffixes to
   differentiate.^[127]

  Advanced SIMD (Neon)Edit

   The Advanced SIMD extension (aka Neon or "MPE" Media Processing Engine) is
   a combined 64- and 128-bit SIMD instruction set that provides standardised
   acceleration for media and signal processing applications. Neon is
   included in all Cortex-A8 devices, but is optional in Cortex-A9
   devices.^[128] Neon can execute MP3 audio decoding on CPUs running at
   10 MHz, and can run the GSM adaptive multi-rate (AMR) speech codec at
   13 MHz. It features a comprehensive instruction set, separate register
   files, and independent execution hardware.^[129] Neon supports 8-, 16-,
   32-, and 64-bit integer and single-precision (32-bit) floating-point data
   and SIMD operations for handling audio and video processing as well as
   graphics and gaming processing. In Neon, the SIMD supports up to
   16 operations at the same time. The Neon hardware shares the same
   floating-point registers as used in VFP. Devices such as the ARM Cortex-A8
   and Cortex-A9 support 128-bit vectors, but will execute with 64 bits at a
   time,^[124] whereas newer Cortex-A15 devices can execute 128 bits at a
   time.^[130]^[131]

   A quirk of Neon in ARMv7 devices is that it flushes all subnormal numbers
   to zero, and as a result the GCC compiler will not use it unless
   -funsafe-math-optimizations, which allows losing denormals, is turned on.
   "Enhanced" Neon defined since ARMv8 does not have this quirk, but as of
   GCC 8.2 the same flag is still required to enable Neon instructions.^[132]
   On the other hand, GCC does consider Neon safe on AArch64 for ARMv8.

   ProjectNe10 is ARM's first open-source project (from its inception; while
   they acquired an older project, now named Mbed TLS). The Ne10 library is a
   set of common, useful functions written in both Neon and C (for
   compatibility). The library was created to allow developers to use Neon
   optimisations without learning Neon, but it also serves as a set of highly
   optimised Neon intrinsic and assembly code examples for common DSP,
   arithmetic, and image processing routines. The source code is available on
   GitHub.^[133]

  ARM Helium technologyEdit

   Helium is the M-Profile Vector Extension (MVE). It adds more than 150
   scalar and vector instructions.^[134]

  Security extensionsEdit

    TrustZone (for Cortex-A profile)Edit

   The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ
   and later application profile architectures. It provides a low-cost
   alternative to adding another dedicated security core to an SoC, by
   providing two virtual processors backed by hardware based access control.
   This lets the application core switch between two states, referred to as
   worlds (to reduce confusion with other names for capability domains), to
   prevent information leaking from the more trusted world to the less
   trusted world. This world switch is generally orthogonal to all other
   capabilities of the processor, thus each world can operate independently
   of the other while using the same core. Memory and peripherals are then
   made aware of the operating world of the core and may use this to provide
   access control to secrets and code on the device.^[135]

   Typically, a rich operating system is run in the less trusted world, with
   smaller security-specialised code in the more trusted world, aiming to
   reduce the attack surface. Typical applications include DRM functionality
   for controlling the use of media on ARM-based devices,^[136] and
   preventing any unapproved use of the device.

   In practice, since the specific implementation details of proprietary
   TrustZone implementations have not been publicly disclosed for review, it
   is unclear what level of assurance is provided for a given threat model,
   but they are not immune from attack.^[137]^[138]

   Open Virtualization^[139] is an open source implementation of the trusted
   world architecture for TrustZone.

   AMD has licensed and incorporated TrustZone technology into its Secure
   Processor Technology.^[140] Enabled in some but not all products, AMD's
   APUs include a Cortex-A5 processor for handling secure
   processing.^[141]^[142]^[143] In fact, the Cortex-A5 TrustZone core had
   been included in earlier AMD products, but was not enabled due to time
   constraints.^[142]

   Samsung Knox uses TrustZone for purposes such as detecting modifications
   to the kernel, storing certificates and attestating keys.^[144]

    TrustZone for ARMv8-M (for Cortex-M profile)Edit

   The Security Extension, marketed as TrustZone for ARMv8-M Technology, was
   introduced in the ARMv8-M architecture. While containing similar concepts
   to TrustZone for ARMv8-A, it has a different architectural design, as
   world switching is performed using branch instructions instead of using
   exceptions. It also supports safe interleaved interrupt handling from
   either world regardless of the current security state. Together these
   features provide low latency calls to the secure world and responsive
   interrupt handling. ARM provides a reference stack of secure world code in
   the form of Trusted Firmware for M and PSA Certified.

  No-execute page protectionEdit

   As of ARMv6, the ARM architecture supports no-execute page protection,
   which is referred to as XN, for eXecute Never.^[145]

  Large Physical Address Extension (LPAE)Edit

   The Large Physical Address Extension (LPAE), which extends the physical
   address size from 32 bits to 40 bits, was added to the ARMv7-A
   architecture in 2011.^[146] Physical address size is larger, 44 bits, in
   Cortex-A75 and Cortex-A65AE.^[147]

  ARMv8-R and ARMv8-MEdit

   The ARMv8-R and ARMv8-M architectures, announced after the ARMv8-A
   architecture, share some features with ARMv8-A. However, ARMv8-M does not
   include any 64-bit AArch64 instructions, and ARMv8-R originally did not
   include any AArch64 instructions; those instructions were added to ARMv8-R
   later.

    ARMv8.1-MEdit

   The ARMv8.1-M architecture, announced in February 2019, is an enhancement
   of the ARMv8-M architecture. It brings new features including:

     * A new vector instruction set extension. The M-Profile Vector Extension
       (MVE), or Helium, is for signal processing and machine learning
       applications.
     * Additional instruction set enhancements for loops and branches (Low
       Overhead Branch Extension).
     * Instructions for half-precision floating-point support.
     * Instruction set enhancement for TrustZone management for Floating
       Point Unit (FPU).
     * New memory attribute in the Memory Protection Unit (MPU).
     * Enhancements in debug including Performance Monitoring Unit (PMU),
       Unprivileged Debug Extension, and additional debug support focus on
       signal processing application developments.
     * Reliability, Availability and Serviceability (RAS) extension.

64/32-bit architectureEdit

   Link: mw-deduplicated-inline-style
   Main article: AArch64
   [IMG] 
   Enlarge
   ARMv8-A Platform with Cortex A57/A53 MPCore big.LITTLE CPU chip

  ARMv8Edit

    ARMv8-AEdit

   Link: mw-deduplicated-inline-style
   See also: Comparison of ARMv8-A cores

   Announced in October 2011,^[3] ARMv8-A (often called ARMv8 while the
   ARMv8-R is also available) represents a fundamental change to the ARM
   architecture. It adds an optional 64-bit architecture (e.g. Cortex-A32 is
   a 32-bit ARMv8-A CPU^[148] while most ARMv8-A CPUs support 64-bit), named
   "AArch64", and the associated new "A64" instruction set. AArch64 provides
   user-space compatibility with ARMv7-A, the 32-bit architecture, therein
   referred to as "AArch32" and the old 32-bit instruction set, now named
   "A32". The Thumb instruction set is referred to as "T32" and has no 64-bit
   counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit
   OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.^[1]
   ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October
   2012.^[70] Apple was the first to release an ARMv8-A compatible core in a
   consumer product (Apple A7 in iPhone 5S). AppliedMicro, using an FPGA, was
   the first to demo ARMv8-A.^[149] The first ARMv8-A SoC from Samsung is the
   Exynos 5433 used in the Galaxy Note 4, which features two clusters of four
   Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will
   run only in AArch32 mode.^[150]

   To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD
   (Neon) standard. It also adds cryptography instructions supporting AES,
   SHA-1/SHA-256 and finite field arithmetic.^[151] AArch64 was introduced in
   ARMv8-A and its subsequent revision. AArch64 is not included in the 32-bit
   ARMv8-R and ARMv8-M architectures.

    ARMv8-REdit

   Optional AArch64 support was added to the ARMv8-R profile, with the first
   ARM core implementing it being the Cortex-R82.^[152] It adds the A64
   instruction set.

  ARMv9Edit

    ARMv9-AEdit

   Announced in March 2021, the updated architecture places a focus on secure
   execution and compartmentalisation.^[153]^[154]

Arm SystemReadyEdit

   Arm SystemReady, formerly named Arm ServerReady, is a certification
   program that helps land the generic off-the-shelf operating systems and
   hypervisors on to the Arm-based systems from datacenter servers to
   industrial edge and IoT devices. The key building blocks of the program
   are the specifications for minimum hardware and firmware requirements that
   the operating systems and hypervisors can rely upon. These specifications
   are:

     * Base System Architecture (BSA) and the market segment specific
       supplements (e.g., Server BSA supplement)
     * Base Boot Requirements (BBR) and Base Boot Security Requirements (BBR)

   These specifications are co-developed by Arm Holdings and its partners in
   the System Architecture Advisory Committee (SystemArchAC).

   Architecture Compliance Suite (ACS) is the test tools that help to check
   the compliance of these specifications. The Arm SystemReady Requirements
   Specification documents the requirements of the certifications.

   This program was introduced by Arm Holdings in 2020 at the first DevSummit
   event. Its predecessor Arm ServerReady was introduced in 2018 at the Arm
   TechCon event. This program currently includes four bands:

     * SystemReady SR: this band is for servers that support operating
       systems and hypervisors that expect UEFI, ACPI and SMBIOS interfaces.
       Windows Server, Red Hat Enterprise Linux and VMware ESXi-Arm require
       these interfaces while other Linux and BSD distros can also
       support.^[clarification needed]
     * SystemReady LS: this band is for servers that hyperscalers use to
       support Linux operating systems that expect LinuxBoot firmware along
       with the ACPI and SMBIOS interfaces.
     * SystemReady ES: this band is for the industrial edge and IoT devices
       that support operating systems and hypervisors that expect UEFI, ACPI
       and SMBIOS interfaces. Windows IoT Enterprise, Red Hat Enterprise
       Linux and VMware ESXi-Arm require these interfaces while other Linux
       and BSD distros can also support.^[clarification needed]
     * SystemReady IR: this band is for the industrial edge and IoT devices
       that support operating systems that expect UEFI and devicetree
       interfaces. Embedded Linux (e.g., Yocto) and some Linux/BSD distros
       (e.g., Fedora, Ubuntu, Debian and OpenSUSE) can also
       support.^[clarification needed]

PSA CertifiedEdit

   PSA Certified, formerly named Platform Security Architecture, is an
   architecture-agnostic security framework and evaluation scheme. It is
   intended to help secure Internet of Things (IoT) devices built on
   system-on-a-chip (SoC) processors.^[155] It was introduced to increase
   security where a full trusted execution environment is too large or
   complex.^[156]

   The architecture was introduced by Arm Holdings in 2017 at the annual
   TechCon event.^[157]^[158] Although the scheme is architecture agnostic,
   it was first implemented on Arm Cortex-M processor cores intended for
   microcontroller use. PSA Certified includes freely available threat models
   and security analyses that demonstrate the process for deciding on
   security features in common IoT products.^[159] It also provides freely
   downloadable application programming interface (API) packages,
   architectural specifications, open-source firmware implementations, and
   related test suites.^[160]

   Following the development of the architecture security framework in 2017,
   the PSA Certified assurance scheme launched two years later at Embedded
   World in 2019.^[161] PSA Certified offers a multi-level security
   evaluation scheme for chip vendors, OS providers and IoT device
   makers.^[162] The Embedded World presentation introduced chip vendors to
   Level 1 Certification. A draft of Level 2 protection was presented at the
   same time.^[163] Level 2 certification became a usable standard in
   February 2020.^[164]

   The certification was created by PSA Joint Stakeholders to enable a
   security-by-design approach for a diverse set of IoT products. PSA
   Certified specifications are implementation and architecture agnostic, as
   a result they can be applied to any chip, software or device.^[165]^[163]
   The certification also removes industry fragmentation for IoT product
   manufacturers and developers.^[166]

Operating system supportEdit

  32-bit operating systemsEdit

    Historical operating systemsEdit

   The first 32-bit ARM-based personal computer, the Acorn Archimedes, was
   originally intended to run an ambitious operating system called ARX. The
   machines shipped with RISC OS which was also used on later ARM-based
   systems from Acorn and other vendors. Some early Acorn machines were also
   able to run a Unix port called RISC iX. (Neither is to be confused with
   RISC/os, a contemporary Unix variant for the MIPS architecture.)

    Embedded operating systemsEdit

   The 32-bit ARM architecture is supported by a large number of embedded and
   real-time operating systems, including:

     * A2
     * Android
     * ChibiOS/RT
     * Deos
     * DRYOS
     * eCos
     * embOS
     * FreeRTOS
     * Integrity
     * Linux
     * Micro-Controller Operating Systems
     * Mbed
     * MINIX 3
     * MQX
     * Nucleus PLUS
     * NuttX
     * Operating System Embedded (OSE)
     * OS-9^[167]
     * Pharos^[168]
     * Plan 9
     * PikeOS^[169]
     * QNX
     * RIOT
     * RTEMS
     * RTXC Quadros
     * SCIOPTA^[170]
     * ThreadX
     * TizenRT
     * T-Kernel
     * VxWorks
     * Windows Embedded Compact
     * Windows 10 IoT Core
     * Zephyr

    Mobile device operating systemsEdit

   The 32-bit ARM architecture is the primary hardware environment for most
   mobile device operating systems such as:

   Link: mw-deduplicated-inline-style
     * Android
     * BlackBerry OS/BlackBerry 10
     * Chrome OS
     * Mobian
     * Sailfish
     * postmarketOS
     * Tizen
     * Ubuntu Touch
     * webOS

   Formerly, but now discontinued:

   Link: mw-deduplicated-inline-style
     * Bada
     * Firefox OS
     * MeeGo
     * iOS 10 and earlier
     * Symbian
     * Windows 10 Mobile
     * Windows RT
     * Windows Phone
     * Windows Mobile

    Desktop/server operating systemsEdit

   The 32-bit ARM architecture is supported by RISC OS and by multiple
   Unix-like operating systems including:

     * FreeBSD
     * NetBSD
     * OpenBSD
     * OpenSolaris^[171]
     * several Linux distributions, such as:
          * Debian
          * Armbian
          * Gentoo
          * Ubuntu
          * Raspberry Pi OS (formerly Raspbian)
          * Slackware

  64-bit operating systemsEdit

    Embedded operating systemsEdit

     * Integrity^[172]
     * OSE^[173]
     * SCIOPTA^[170]
     * seL4^[174]
     * Pharos^[168]
     * FreeRTOS
     * QNX^[175]
     * Zephyr

    Mobile device operating systemsEdit

     * Android supports ARMv8-A in Android Lollipop (5.0) and later.
     * iOS supports ARMv8-A in iOS 7 and later on 64-bit Apple SoCs. iOS 11
       and later only supports 64-bit ARM processors and applications.
     * Mobian
     * PostmarketOS
     * Arch Linux ARM
     * Manjaro ARM

    Desktop/server operating systemsEdit

     * Support for ARMv8-A was merged into the Linux kernel version 3.7 in
       late 2012.^[176] ARMv8-A is supported by a number of Linux
       distributions, such as:
          * Debian^[177]^[178]
          * Armbian
          * Alpine Linux
          * Ubuntu^[179]
          * Fedora^[180]
          * openSUSE^[181]
          * SUSE Linux Enterprise^[182]
          * RHEL^[183]
          * Raspberry Pi OS (formerly Raspbian. Beta version as of early
            2022)
     * Support for ARMv8-A was merged into FreeBSD in late 2014.^[184]
     * OpenBSD has experimental ARMv8 support as of 2017.^[185]
     * NetBSD has ARMv8 support as of early 2018.^[186]
     * Windows 10 – runs 32-bit "x86 and 32-bit ARM applications",^[187] as
       well as native ARM64 desktop apps.^[188]^[189] Support for 64-bit ARM
       apps in the Microsoft Store has been available since November
       2018.^[190]
     * macOS has ARM support starting with macOS Big Sur as of late
       2020.^[191] Rosetta 2 adds support for x86-64 applications but not
       virtualization of x86-64 computer platforms.^[192]

  Porting to 32- or 64-bit ARM operating systemsEdit

   Windows applications recompiled for ARM and linked with Winelib, from the
   Wine project, can run on 32-bit or 64-bit ARM in Linux, FreeBSD, or other
   compatible operating systems.^[193]^[194] x86 binaries, e.g. when not
   specially compiled for ARM, have been demonstrated on ARM using QEMU with
   Wine (on Linux and more),^[citation needed] but do not work at full speed
   or same capability as with Winelib.

NotesEdit

   Link: mw-deduplicated-inline-style
    1. ^ Using 32-bit words, 4 Mbit/second corresponds to 1 MIPS.
    2. ^ Available references do not mention which design team this was, but
       given the timing and known history of designs of the era, it is likely
       this was the National Semiconductor team whose NS32016 suffered from a
       large number of bugs.
    3. ^ Matt Evans notes that it appears the faster versions were simply
       binned higher, and appear to have no underlying changes.^[36]

See alsoEdit

     * icon Electronics portal
     * RISC
     * RISC-V
     * Apple silicon
     * ARM big.LITTLE – ARM's heterogeneous computing architecture
          * DynamIQ
     * ARM Accredited Engineer – certification program
     * ARMulator – an instruction set simulator
     * Amber (processor core) – an open-source ARM-compatible processor core
     * AMULET microprocessor – an asynchronous implementation of the ARM
       architecture
     * Comparison of ARMv7-A cores
     * Comparison of ARMv8-A cores
     * Unicore – a 32-register architecture based heavily on a 32-bit ARM
     * Meltdown (security vulnerability)^[195]
     * Spectre (security vulnerability)

ReferencesEdit

  CitationsEdit

   Link: mw-deduplicated-inline-style
    1. ^ ^a ^b ^c ^d ^e Grisenthwaite, Richard (2011). "ARMv8-A Technology
       Preview" (PDF). Archived from the original (PDF) on 11 November 2011.
       Retrieved 31 October 2011.
    2. ^
       Link: mw-deduplicated-inline-style
       "Procedure Call Standard for the ARM Architecture" (PDF). Arm
       Holdings. 30 November 2013. Retrieved 27 May 2013.
    3. ^ ^a ^b
       Link: mw-deduplicated-inline-style
       "ARM Discloses Technical Details of the Next Version of the ARM
       Architecture" (Press release). Arm Holdings. 27 October 2011. Archived
       from the original on 1 January 2019. Retrieved 20 September 2013.
    4. ^
       Link: mw-deduplicated-inline-style
       "Announcing the ARM Neoverse N1 Platform". community.arm.com.
       Retrieved 8 April 2020.
    5. ^ ^a ^b "Some facts about the Acorn RISC Machine" Roger Wilson posting
       to comp.arch, 2 November 1988. Retrieved 25 May 2007.
    6. ^ ^a ^b
       Link: mw-deduplicated-inline-style
       Hachman, Mark (14 October 2002). "ARM Cores Climb into 3G Territory".
       ExtremeTech. Retrieved 24 May 2018.
    7. ^
       Link: mw-deduplicated-inline-style
       Turley, Jim (18 December 2002). "The Two Percent Solution". Embedded.
       Retrieved 24 May 2018.
    8. ^
       Link: mw-deduplicated-inline-style
       Cutress, Ian (22 June 2020). "New #1 Supercomputer: Fujitsu's Fugaku
       and A64FX take Arm to the Top with 415 PetaFLOPs". www.anandtech.com.
       Retrieved 25 January 2021.
    9. ^
       Link: mw-deduplicated-inline-style
       "Arm Partners Have Shipped 200 Billion Chips". Arm (Press release).
       Retrieved 3 November 2021.
   10. ^
       Link: mw-deduplicated-inline-style
       "Architecting a smart world and powering Artificial Intelligence:
       ARM". The Silicon Review. 2019. Retrieved 8 April 2020.
   11. ^
       Link: mw-deduplicated-inline-style
       "Enabling Mass IoT connectivity as ARM partners ship 100 billion
       chips". community.arm.com. Retrieved 8 April 2020. the cumulative
       deployment of 100 billion chips, half of which shipped in the last
       four years. [..] why not a trillion or more? That is our target,
       seeing a trillion connected devices deployed over the next two
       decades.
   12. ^
       Link: mw-deduplicated-inline-style
       "MCU Market on Migration Path to 32-bit and ARM-based Devices: 32-bit
       tops in sales; 16-bit leads in unit shipments". IC Insights. 25 April
       2013. Retrieved 1 July 2014.
   13. ^
       Link: mw-deduplicated-inline-style
       Turley, Jim (2002). "The Two Percent Solution". embedded.com.
   14. ^
       Link: mw-deduplicated-inline-style
       "Arm Holdings eager for PC and server expansion". The Register. 1
       February 2011.
   15. ^
       Link: mw-deduplicated-inline-style
       McGuire-Balanza, Kerry (11 May 2010). "ARM from zero to billions in 25
       short years". Arm Holdings. Retrieved 8 November 2012.
   16. ^
       Link: mw-deduplicated-inline-style
       Fairbairn, Douglas (31 January 2012). "Oral History of Sophie Wilson"
       (PDF). Archived (PDF) from the original on 3 March 2016. Retrieved 2
       February 2016.
   17. ^
       Link: mw-deduplicated-inline-style
       Smith, Tony (30 November 2011). "The BBC Micro turns 30". The Register
       Hardware. Archived from the original on 12 December 2011. Retrieved 12
       December 2011.
   18. ^
       Link: mw-deduplicated-inline-style
       Polsson, Ken. "Chronology of Microprocessors". Processortimeline.info.
       Retrieved 27 September 2013.
   19. ^
       Link: mw-deduplicated-inline-style
       Leedy, Glenn (April 1983). "The National Semiconductor NS16000
       Microprocessor Family". Byte. pp. 53–66. Retrieved 22 August 2020.
   20. ^ Evans 2019, 6:00.
   21. ^
       Link: mw-deduplicated-inline-style
       Manners, David (29 April 1998). "ARM's way". Electronics Weekly.
       Archived from the original on 29 July 2012. Retrieved 26 October 2012.
   22. ^ Evans 2019, 5:30.
   23. ^ ^a ^b Evans 2019, 7:45.
   24. ^ Evans 2019, 8:30.
   25. ^
       Link: mw-deduplicated-inline-style
       Sophie Wilson at Alt Party 2009 (Part 3/8). Archived from the original
       on 11 December 2021.
   26. ^
       Link: mw-deduplicated-inline-style
       Chisnall, David (23 August 2010). Understanding ARM Architectures.
       Retrieved 26 May 2013.
   27. ^ Evans 2019, 9:00.
   28. ^
       Link: mw-deduplicated-inline-style
       Furber, Stephen B. (2000). ARM system-on-chip architecture. Boston:
       Addison-Wesley. ISBN 0-201-67519-6.
   29. ^ Evans 2019, 9:50.
   30. ^ Evans 2019, 23:30.
   31. ^ Evans 2019, 26:00.
   32. ^
       Link: mw-deduplicated-inline-style
       "ARM Instruction Set design history with Sophie Wilson (Part 3)". 10
       May 2015. Archived from the original on 11 December 2021. Retrieved 25
       May 2020 – via YouTube.
   33. ^
       Link: mw-deduplicated-inline-style
       "Oral History of Sophie Wilson – 2012 Computer History Museum Fellow"
       (PDF). Computer History Museum. 31 January 2012. Retrieved 25 May
       2020.
   34. ^
       Link: mw-deduplicated-inline-style
       Harker, T. (Summer 2009). "ARM gets serious about IP (Second in a
       two-part series [Associated Editors' View]". IEEE Solid-State Circuits
       Magazine. 1 (3): 8–69. doi:10.1109/MSSC.2009.933674. ISSN 1943-0590.
       S2CID 36567166.
   35. ^ Evans 2019, 20:30.
   36. ^ Evans 2019, 22:00.
   37. ^ Evans 2019, 21:30.
   38. ^ Evans 2019, 22:0030.
   39. ^ ^a ^b Evans 2019, 14:00.
   40. ^
       Link: mw-deduplicated-inline-style
       Levy, Markus. "The History of The ARM Architecture: From Inception to
       IPO" (PDF). Retrieved 14 March 2013.
   41. ^
       Link: mw-deduplicated-inline-style
       Santanu Chattopadhyay (2010). Embedded System Design. PHI Learning
       Pvt. Ltd. p. 9. ISBN 978-81-203-4024-4.
   42. ^
       Link: mw-deduplicated-inline-style
       Richard Murray. "32 bit operation".
   43. ^ ARM milestones, ARM company website. Retrieved 8 April 2015
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       Archived from the original on 11 December 2021.

Further readingEdit

   Link: mw-deduplicated-inline-style
   See also: List of books about ARM Cortex-M

External linksEdit

   Wikimedia Commons has media related to ARM architecture. 

     * Official website Edit this at Wikidata , ARM Ltd.

   Architecture manuals

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       ARM Limited (2005). "ARM Architecture Reference Manual".
       documentation-service.arm.com. Retrieved 16 July 2021. - covers ARMv4,
       ARMv4T, ARMv5T, (ARMv5TExP), ARMv5TE, ARMv5TEJ, and ARMv6
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       documentation. Retrieved 17 July 2021.
     * Link: mw-deduplicated-inline-style
       ARM Limited (2018). "ARM Architecture Reference Manual ARMv7-A and
       ARMv7-R edition". ARM documentation. Retrieved 17 July 2021.
     * Link: mw-deduplicated-inline-style
       ARM Limited (2021). "Arm Architecture Reference Manual Armv8, for
       Armv8-A architecture profile". ARM documentation. Retrieved 17 July
       2021.
     * Link: mw-deduplicated-inline-style
       ARM Limited (2021). "ARM Architecture Reference Manual Supplement -
       ARMv8, for the ARMv8-R AArch32 architecture profile". ARM
       documentation. Retrieved 17 July 2021.
     * Link: mw-deduplicated-inline-style
       ARM Limited (2021). "Arm Architecture Reference Manual Supplement -
       Armv8, for Armv8-R AArch64 architecture profile". ARM documentation.
       Retrieved 17 July 2021.
     * Link: mw-deduplicated-inline-style
       ARM Limited (2021). "Armv8-M Architecture Reference Manual". ARM
       documentation. Retrieved 17 July 2021.
     * Link: mw-deduplicated-inline-style
       ARM Limited (2021). "Arm Armv9-A A64 Instruction Set Architecture".
       ARM documentation. Retrieved 17 July 2021.
     * ARM Virtualization Extensions

   Quick Reference Cards

     * Instructions: Thumb, ARM and Thumb-2, Vector Floating Point
     * Opcodes: Thumb, Thumb, ARM, ARM, GNU Assembler Directives
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