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                                     x86-64

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   "AMD64" and "Intel 64" redirect here. For the Intel 64-bit architecture in
   Itanium chips, see IA-64.
   Link: mw-deduplicated-inline-style
   "x64" redirects here. For the New York City bus route, see X64 (New York
   City bus).

   x86-64 (also known as x64, x86_64, AMD64, and Intel 64)^[note 1] is a
   64-bit version of the x86 instruction set, first released in 1999. It
   introduced two new modes of operation, 64-bit mode and compatibility mode,
   along with a new 4-level paging mode.

   [IMG]
   Enlarge
   AMD Opteron, the first CPU to introduce the x86-64 extensions in April
   2003
   [IMG]
   Enlarge
   The five-volume set of the x86-64 Architecture Programmer's Manual, as
   published and distributed by AMD in 2002

   With 64-bit mode and the new paging mode, it supports vastly larger
   amounts of virtual memory and physical memory than was possible on its
   32-bit predecessors, allowing programs to store larger amounts of data in
   memory. x86-64 also expands general-purpose registers to 64-bit, and
   expands the number of them from 8 (some of which had limited or fixed
   functionality, e.g. for stack management) to 16 (fully general), and
   provides numerous other enhancements. Floating-point arithmetic is
   supported via mandatory SSE2-like instructions, and x87/MMX style
   registers are generally not used (but still available even in 64-bit
   mode); instead, a set of 16 vector registers, 128 bits each, is used.
   (Each register can store one or two double-precision numbers or one to
   four single-precision numbers, or various integer formats.) In 64-bit
   mode, instructions are modified to support 64-bit operands and 64-bit
   addressing mode.

   The compatibility mode defined in the architecture allows 16- and 32-bit
   user applications to run unmodified, coexisting with 64-bit applications
   if the 64-bit operating system supports them.^[11]^[note 2] As the full
   x86 16-bit and 32-bit instruction sets remain implemented in hardware
   without any intervening emulation, these older executables can run with
   little or no performance penalty,^[13] while newer or modified
   applications can take advantage of new features of the processor design to
   achieve performance improvements. Also, a processor supporting x86-64
   still powers on in real mode for full backward compatibility with the
   8086, as x86 processors supporting protected mode have done since the
   80286.

   The original specification, created by AMD and released in 2000, has been
   implemented by AMD, Intel, and VIA. The AMD K8 microarchitecture, in the
   Opteron and Athlon 64 processors, was the first to implement it. This was
   the first significant addition to the x86 architecture designed by a
   company other than Intel. Intel was forced to follow suit and introduced a
   modified NetBurst family which was software-compatible with AMD's
   specification. VIA Technologies introduced x86-64 in their VIA Isaiah
   architecture, with the VIA Nano.

   The x86-64 architecture is distinct from the Intel Itanium architecture
   (formerly IA-64). The architectures are not compatible on the native
   instruction set level, and operating systems and applications compiled for
   one cannot be run on the other.

Contents

     * 1 AMD64
          * 1.1 History
          * 1.2 Implementations
          * 1.3 Architectural features
          * 1.4 Virtual address space details
               * 1.4.1 Canonical form addresses
               * 1.4.2 Page table structure
               * 1.4.3 Operating system limits
          * 1.5 Physical address space details
          * 1.6 Operating modes
               * 1.6.1 Long mode
               * 1.6.2 Legacy mode
                    * 1.6.2.1 Protected mode
                    * 1.6.2.2 Real mode
     * 2 Intel 64
          * 2.1 History
          * 2.2 Implementations
     * 3 VIA's x86-64 implementation
     * 4 Microarchitecture levels
     * 5 Differences between AMD64 and Intel 64
          * 5.1 Recent implementations
          * 5.2 Older implementations
     * 6 Adoption
     * 7 Operating system compatibility and characteristics
          * 7.1 BSD
               * 7.1.1 DragonFly BSD
               * 7.1.2 FreeBSD
               * 7.1.3 NetBSD
               * 7.1.4 OpenBSD
          * 7.2 DOS
          * 7.3 Linux
          * 7.4 macOS
          * 7.5 Solaris
          * 7.6 Windows
     * 8 Video game consoles
     * 9 Industry naming conventions
     * 10 Licensing
     * 11 See also
     * 12 Notes
     * 13 References
     * 14 External links

AMD64Edit

   [IMG] 
   Enlarge
   AMD64 logo

  HistoryEdit

   AMD64 (also variously referred to by AMD in their literature and
   documentation as “AMD 64-bit Technology” and “AMD x86-64 Architecture”)
   was created as an alternative to the radically different IA-64
   architecture designed by Intel and Hewlett-Packard, which was
   backward-incompatible with IA-32, the 32-bit version of the x86
   architecture. Originally announced in 1999^[14] with a full specification
   available in August 2000,^[15] the AMD64 architecture was positioned by
   AMD from the beginning as an evolutionary way to add 64-bit computing
   capabilities to the existing x86 architecture while supporting legacy
   32-bit x86 code, as opposed to Intel's approach of creating an entirely
   new 64-bit architecture with IA-64.

   The first AMD64-based processor, the Opteron, was released in April 2003.

  ImplementationsEdit

   AMD's processors implementing the AMD64 architecture include Opteron,
   Athlon 64, Athlon 64 X2, Athlon 64 FX, Athlon II (followed by "X2", "X3",
   or "X4" to indicate the number of cores, and XLT models), Turion 64,
   Turion 64 X2, Sempron ("Palermo" E6 stepping and all "Manila" models),
   Phenom (followed by "X3" or "X4" to indicate the number of cores), Phenom
   II (followed by "X2", "X3", "X4" or "X6" to indicate the number of cores),
   FX, Fusion/APU and Ryzen/Epyc.^[citation needed]

  Architectural featuresEdit

   The primary defining characteristic of AMD64 is the availability of 64-bit
   general-purpose processor registers (for example, rax), 64-bit integer
   arithmetic and logical operations, and 64-bit virtual addresses.^[citation
   needed] The designers took the opportunity to make other improvements as
   well.

   Notable changes in the 64-bit extensions include:

   64-bit integer capability
           All general-purpose registers (GPRs) are expanded from 32 bits to
           64 bits, and all arithmetic and logical operations,
           memory-to-register and register-to-memory operations, etc., can
           operate directly on 64-bit integers. Pushes and pops on the stack
           default to 8-byte strides, and pointers are 8 bytes wide.

   Additional registers
           In addition to increasing the size of the general-purpose
           registers, the number of named general-purpose registers is
           increased from eight (i.e.
           Link: mw-deduplicated-inline-style
           eax,
           Link: mw-deduplicated-inline-style
           ecx,
           Link: mw-deduplicated-inline-style
           edx,
           Link: mw-deduplicated-inline-style
           ebx,
           Link: mw-deduplicated-inline-style
           esp,
           Link: mw-deduplicated-inline-style
           ebp,
           Link: mw-deduplicated-inline-style
           esi,
           Link: mw-deduplicated-inline-style
           edi) in x86 to 16 (i.e.
           Link: mw-deduplicated-inline-style
           rax,
           Link: mw-deduplicated-inline-style
           rcx,
           Link: mw-deduplicated-inline-style
           rdx,
           Link: mw-deduplicated-inline-style
           rbx,
           Link: mw-deduplicated-inline-style
           rsp,
           Link: mw-deduplicated-inline-style
           rbp,
           Link: mw-deduplicated-inline-style
           rsi,
           Link: mw-deduplicated-inline-style
           rdi,
           Link: mw-deduplicated-inline-style
           r8,
           Link: mw-deduplicated-inline-style
           r9,
           Link: mw-deduplicated-inline-style
           r10,
           Link: mw-deduplicated-inline-style
           r11,
           Link: mw-deduplicated-inline-style
           r12,
           Link: mw-deduplicated-inline-style
           r13,
           Link: mw-deduplicated-inline-style
           r14,
           Link: mw-deduplicated-inline-style
           r15). It is therefore possible to keep more local variables in
           registers rather than on the stack, and to let registers hold
           frequently accessed constants; arguments for small and fast
           subroutines may also be passed in registers to a greater extent.
           AMD64 still has fewer registers than many RISC instruction sets
           (e.g. PA-RISC, Power ISA, and MIPS have 32 GPRs; Alpha, 64-bit
           ARM, and SPARC have 31) or VLIW-like machines such as the IA-64
           (which has 128 registers). However, an AMD64 implementation may
           have far more internal registers than the number of architectural
           registers exposed by the instruction set (see register renaming).
           (For example, AMD Zen cores have 168 64-bit integer and 160
           128-bit vector floating-point physical internal registers.)

   Additional XMM (SSE) registers
           Similarly, the number of 128-bit XMM registers (used for Streaming
           SIMD instructions) is also increased from 8 to 16.
           The traditional x87 FPU register stack is not included in the
           register file size extension in 64-bit mode, compared with the XMM
           registers used by SSE2, which did get extended. The x87 register
           stack is not a simple register file although it does allow direct
           access to individual registers by low cost exchange operations.

   Larger virtual address space
           The AMD64 architecture defines a 64-bit virtual address format, of
           which the low-order 48 bits are used in current
           implementations.^[11]^: 120  This allows up to 256 TiB (2^48
           bytes) of virtual address space. The architecture definition
           allows this limit to be raised in future implementations to the
           full 64 bits,^[11]^: 2 ^: 3 ^: 13 ^: 117 ^: 120  extending the
           virtual address space to 16 EiB (2^64 bytes).^[16] This is
           compared to just 4 GiB (2^32 bytes) for the x86.^[17]
           This means that very large files can be operated on by mapping the
           entire file into the process's address space (which is often much
           faster than working with file read/write calls), rather than
           having to map regions of the file into and out of the address
           space.

   Larger physical address space
           The original implementation of the AMD64 architecture implemented
           40-bit physical addresses and so could address up to 1 TiB (2^40
           bytes) of RAM.^[11]^: 24  Current implementations of the AMD64
           architecture (starting from AMD 10h microarchitecture) extend this
           to 48-bit physical addresses^[18] and therefore can address up to
           256 TiB (2^48 bytes) of RAM. The architecture permits extending
           this to 52 bits in the future^[11]^: 24 ^[19] (limited by the page
           table entry format);^[11]^: 131  this would allow addressing of up
           to 4 PiB of RAM. For comparison, 32-bit x86 processors are limited
           to 64 GiB of RAM in Physical Address Extension (PAE) mode,^[20] or
           4 GiB of RAM without PAE mode.^[11]^: 4 

   Larger physical address space in legacy mode
           When operating in legacy mode the AMD64 architecture supports
           Physical Address Extension (PAE) mode, as do most current x86
           processors, but AMD64 extends PAE from 36 bits to an architectural
           limit of 52 bits of physical address. Any implementation,
           therefore, allows the same physical address limit as under long
           mode.^[11]^: 24 

   Instruction pointer relative data access
           Instructions can now reference data relative to the instruction
           pointer (RIP register). This makes position-independent code, as
           is often used in shared libraries and code loaded at run time,
           more efficient.

   SSE instructions
           The original AMD64 architecture adopted Intel's SSE and SSE2 as
           core instructions. These instruction sets provide a vector
           supplement to the scalar x87 FPU, for the single-precision and
           double-precision data types. SSE2 also offers integer vector
           operations, for data types ranging from 8bit to 64bit precision.
           This makes the vector capabilities of the architecture on par with
           those of the most advanced x86 processors of its time. These
           instructions can also be used in 32-bit mode. The proliferation of
           64-bit processors has made these vector capabilities ubiquitous in
           home computers, allowing the improvement of the standards of
           32-bit applications. The 32-bit edition of Windows 8, for example,
           requires the presence of SSE2 instructions.^[21] SSE3 instructions
           and later Streaming SIMD Extensions instruction sets are not
           standard features of the architecture.

   No-Execute bit
           The No-Execute bit or NX bit (bit 63 of the page table entry)
           allows the operating system to specify which pages of virtual
           address space can contain executable code and which cannot. An
           attempt to execute code from a page tagged "no execute" will
           result in a memory access violation, similar to an attempt to
           write to a read-only page. This should make it more difficult for
           malicious code to take control of the system via "buffer overrun"
           or "unchecked buffer" attacks. A similar feature has been
           available on x86 processors since the 80286 as an attribute of
           segment descriptors; however, this works only on an entire segment
           at a time.
           Segmented addressing has long been considered an obsolete mode of
           operation, and all current PC operating systems in effect bypass
           it, setting all segments to a base address of zero and (in their
           32-bit implementation) a size of 4 GiB. AMD was the first
           x86-family vendor to implement no-execute in linear addressing
           mode. The feature is also available in legacy mode on AMD64
           processors, and recent Intel x86 processors, when PAE is used.

   Removal of older features
           A few "system programming" features of the x86 architecture were
           either unused or underused in modern operating systems and are
           either not available on AMD64 in long (64-bit and compatibility)
           mode, or exist only in limited form. These include segmented
           addressing (although the FS and GS segments are retained in
           vestigial form for use as extra-base pointers to operating system
           structures),^[11]^: 70  the task state switch mechanism, and
           virtual 8086 mode. These features remain fully implemented in
           "legacy mode", allowing these processors to run 32-bit and 16-bit
           operating systems without modifications. Some instructions that
           proved to be rarely useful are not supported in 64-bit mode,
           including saving/restoring of segment registers on the stack,
           saving/restoring of all registers (PUSHA/POPA), decimal
           arithmetic, BOUND and INTO instructions, and "far" jumps and calls
           with immediate operands.

  Virtual address space detailsEdit

    Canonical form addressesEdit

   Canonical address space implementations (diagrams not to scale)
   [IMG] 
   Current 48-bit implementation
   [IMG] 
   57-bit implementation
   [IMG] 
   64-bit implementation

   Although virtual addresses are 64 bits wide in 64-bit mode, current
   implementations (and all chips that are known to be in the planning
   stages) do not allow the entire virtual address space of 2^64 bytes
   (16 EiB) to be used. This would be approximately four billion times the
   size of the virtual address space on 32-bit machines. Most operating
   systems and applications will not need such a large address space for the
   foreseeable future, so implementing such wide virtual addresses would
   simply increase the complexity and cost of address translation with no
   real benefit. AMD, therefore, decided that, in the first implementations
   of the architecture, only the least significant 48 bits of a virtual
   address would actually be used in address translation (page table
   lookup).^[11]^: 120 

   In addition, the AMD specification requires that the most significant 16
   bits of any virtual address, bits 48 through 63, must be copies of bit 47
   (in a manner akin to sign extension). If this requirement is not met, the
   processor will raise an exception.^[11]^: 131  Addresses complying with
   this rule are referred to as "canonical form."^[11]^: 130  Canonical form
   addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000
   through FFFFFFFF'FFFFFFFF, for a total of 256 TiB of usable virtual
   address space. This is still 65,536 times larger than the virtual 4 GiB
   address space of 32-bit machines.

   This feature eases later scalability to true 64-bit addressing. Many
   operating systems (including, but not limited to, the Windows NT family)
   take the higher-addressed half of the address space (named kernel space)
   for themselves and leave the lower-addressed half (user space) for
   application code, user mode stacks, heaps, and other data regions.^[22]
   The "canonical address" design ensures that every AMD64 compliant
   implementation has, in effect, two memory halves: the lower half starts at
   00000000'00000000 and "grows upwards" as more virtual address bits become
   available, while the higher half is "docked" to the top of the address
   space and grows downwards. Also, enforcing the "canonical form" of
   addresses by checking the unused address bits prevents their use by the
   operating system in tagged pointers as flags, privilege markers, etc., as
   such use could become problematic when the architecture is extended to
   implement more virtual address bits.

   The first versions of Windows for x64 did not even use the full 256 TiB;
   they were restricted to just 8 TiB of user space and 8 TiB of kernel
   space.^[22] Windows did not support the entire 48-bit address space until
   Windows 8.1, which was released in October 2013.^[22]

    Page table structureEdit

   The 64-bit addressing mode ("long mode") is a superset of Physical Address
   Extensions (PAE); because of this, page sizes may be 4 KiB (2^12 bytes) or
   2 MiB (2^21 bytes).^[11]^: 120  Long mode also supports page sizes of
   1 GiB (2^30 bytes).^[11]^: 120  Rather than the three-level page table
   system used by systems in PAE mode, systems running in long mode use four
   levels of page table: PAE's Page-Directory Pointer Table is extended from
   four entries to 512, and an additional Page-Map Level 4 (PML4) Table is
   added, containing 512 entries in 48-bit implementations.^[11]^: 131  A
   full mapping hierarchy of 4 KiB pages for the whole 48-bit space would
   take a bit more than 512 GiB of memory (about 0.195% of the 256 TiB
   virtual space).

   Intel has implemented a scheme with a 5-level page table, which allows
   Intel 64 processors to support a 57-bit virtual address space.^[23]
   Further extensions may allow full 64-bit virtual address space and
   physical memory by expanding the page table entry size to 128-bit, and
   reduce page walks in the 5-level hierarchy by using a larger 64 KiB page
   allocation size that still supports 4 KiB page operations for backward
   compatibility.^[24]

    Operating system limitsEdit

   The operating system can also limit the virtual address space. Details,
   where applicable, are given in the "Operating system compatibility and
   characteristics" section.

  Physical address space detailsEdit

   Current AMD64 processors support a physical address space of up to 2^48
   bytes of RAM, or 256 TiB.^[18] However, as of 2020, there were no known
   x86-64 motherboards that support 256 TiB of
   RAM.^[25]^[26]^[27]^[28]^[failed verification] The operating system may
   place additional limits on the amount of RAM that is usable or supported.
   Details on this point are given in the "Operating system compatibility and
   characteristics" section of this article.

  Operating modesEdit

   The architecture has two primary modes of operation: long mode and legacy
   mode.

Operating                                     Size (in bits)                     
                     Operating      Type of             operands No. of          
mode   sub-mode      system         code      addresses (default general-purpose 
                     required       being run           in       registers
                                                        italics) 
                     64-bit OS,                                                  
                     64-bit UEFI                                 
                     firmware, or   
                     the previous                       8, 16,
       64-bit mode   two            64-bit    64        32, 64   16
                     interacting    
Long                 via a 64-bit   
mode                 firmware's     
                     UEFI interface 
                                    32-bit    32        8, 16,   8               
       Compatibility Bootloader or                      32       
       mode          64-bit OS      16-bit              8, 16,                   
                                    protected 16        32       8
                                    mode      
                     Bootloader,                                                 
                     32-bit OS,                                  
                     32-bit UEFI    
                     firmware, or                       8, 16,
                     the latter two 32-bit    32        32       8
       Protected     interacting    
       mode          via the        
                     firmware's     
                     UEFI interface 
                     16-bit         16-bit              8, 16,                   
                     protected mode protected 16        32^[m 1] 8
Legacy               OS             mode      
mode   Virtual 8086  16-bit         subset of           8, 16,                   
       mode          protected mode real mode 16        32^[m 1] 8
                     or 32-bit OS   
       Unreal mode   Bootloader or  real mode 16, 20,   8, 16,   8               
                     real mode OS             32        32^[m 1] 
                     Bootloader,                                                 
                     real mode OS,                               
                     or any OS      
       Real mode     interfacing    real mode 16, 20,   8, 16,   8
                     with a                   21        32^[m 1]
                     firmware's     
                     BIOS           
                     interface^[29] 

    1. ^ ^a ^b ^c ^d Note that 16-bit code written for the 80286 and below
       does not use 32-bit operand instructions. Code written for the 80386
       and above can use the operand-size override prefix (0x66). Normally
       this prefix is used by protected and long mode code for the purpose of
       using 16-bit operands, as that code would be running in a code segment
       with a default operand size of 32 bits. In real mode, the default
       operand size is 16 bits, so the 0x66 prefix is interpreted
       differently, changing operand size to 32 bits.
   [IMG] 
   Enlarge
   State diagram of the x86-64 operating modes

    Long modeEdit

   Link: mw-deduplicated-inline-style
   Main article: Long mode

   Long mode is the architecture's intended primary mode of operation; it is
   a combination of the processor's native 64-bit mode and a combined 32-bit
   and 16-bit compatibility mode. It is used by 64-bit operating systems.
   Under a 64-bit operating system, 64-bit programs run under 64-bit mode,
   and 32-bit and 16-bit protected mode applications (that do not need to use
   either real mode or virtual 8086 mode in order to execute at any time) run
   under compatibility mode. Real-mode programs and programs that use virtual
   8086 mode at any time cannot be run in long mode unless those modes are
   emulated in software.^[11]^: 11  However, such programs may be started
   from an operating system running in long mode on processors supporting
   VT-x or AMD-V by creating a virtual processor running in the desired mode.

   Since the basic instruction set is the same, there is almost no
   performance penalty for executing protected mode x86 code. This is unlike
   Intel's IA-64, where differences in the underlying instruction set mean
   that running 32-bit code must be done either in emulation of x86 (making
   the process slower) or with a dedicated x86 coprocessor. However, on the
   x86-64 platform, many x86 applications could benefit from a 64-bit
   recompile, due to the additional registers in 64-bit code and guaranteed
   SSE2-based FPU support, which a compiler can use for optimization.
   However, applications that regularly handle integers wider than 32 bits,
   such as cryptographic algorithms, will need a rewrite of the code handling
   the huge integers in order to take advantage of the 64-bit registers.

    Legacy modeEdit

   Legacy mode is the mode that the processor is in when it is not in long
   mode.^[11]^: 14  In this mode, the processor acts like an older x86
   processor, and only 16-bit and 32-bit code can be executed. Legacy mode
   allows for a maximum of 32 bit virtual addressing which limits the virtual
   address space to 4 GiB.^[11]^: 14 ^: 24 ^: 118  64-bit programs cannot be
   run from legacy mode.

      Protected modeEdit

   Protected mode is made into a submode of legacy mode.^[11]^: 14  It is the
   submode that 32-bit operating systems and 16-bit protected mode operating
   systems operate in when running on an x86-64 CPU.^[11]^: 14 

      Real modeEdit

   Real mode is the initial mode of operation when the processor is
   initialized, and is a submode of legacy mode. It is backwards compatible
   with the original Intel 8086 and Intel 8088 processors. Real mode is
   primarily used today by operating system bootloaders, which are required
   by the architecture to configure virtual memory details before
   transitioning to higher modes. This mode is also used by any operating
   system that needs to communicate with the system firmware with a
   traditional BIOS-style interface.^[29]

Intel 64Edit

   Intel 64 is Intel's implementation of x86-64, used and implemented in
   various processors made by Intel.

  HistoryEdit

   Historically, AMD has developed and produced processors with instruction
   sets patterned after Intel's original designs, but with x86-64, roles were
   reversed: Intel found itself in the position of adopting the ISA that AMD
   created as an extension to Intel's own x86 processor line.

   Intel's project was originally codenamed Yamhill (after the Yamhill River
   in Oregon's Willamette Valley).^[citation needed] After several years of
   denying its existence, Intel announced at the February 2004 IDF that the
   project was indeed underway. Intel's chairman at the time, Craig Barrett,
   admitted that this was one of their worst-kept secrets.^[30]^[31]

   Intel's name for this instruction set has changed several times. The name
   used at the IDF was CT^[32] (presumably^[original research?] for Clackamas
   Technology, another codename from an Oregon river); within weeks they
   began referring to it as IA-32e (for IA-32 extensions) and in March 2004
   unveiled the "official" name EM64T (Extended Memory 64 Technology). In
   late 2006 Intel began instead using the name Intel 64 for its
   implementation, paralleling AMD's use of the name AMD64.^[33]

   The first processor to implement Intel 64 was the multi-socket processor
   Xeon code-named Nocona in June 2004. In contrast, the initial Prescott
   chips (February 2004) did not enable this feature. Intel subsequently
   began selling Intel 64-enabled Pentium 4s using the E0 revision of the
   Prescott core, being sold on the OEM market as the Pentium 4, model F. The
   E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit)
   to Intel 64, and has been included in then current Xeon code-named
   Irwindale. Intel's official launch of Intel 64 (under the name EM64T at
   that time) in mainstream desktop processors was the N0 stepping
   Prescott-2M.

   The first Intel mobile processor implementing Intel 64 is the Merom
   version of the Core 2 processor, which was released on July 27, 2006. None
   of Intel's earlier notebook CPUs (Core Duo, Pentium M, Celeron M, Mobile
   Pentium 4) implement Intel 64.

  ImplementationsEdit

   Intel's processors implementing the Intel64 architecture include the
   Pentium 4 F-series/5x1 series, 506, and 516, Celeron D models 3x1, 3x6,
   355, 347, 352, 360, and 365 and all later Celerons, all models of Xeon
   since "Nocona", all models of Pentium Dual-Core processors since
   "Merom-2M", the Atom 230, 330, D410, D425, D510, D525, N450, N455, N470,
   N475, N550, N570, N2600 and N2800, all versions of the Pentium D, Pentium
   Extreme Edition, Core 2, Core i9, Core i7, Core i5, and Core i3
   processors, and the Xeon Phi 7200 series processors.

VIA's x86-64 implementationEdit

   VIA Technologies introduced their first implementation of the x86-64
   architecture in 2008 after five years of development by its CPU division,
   Centaur Technology.^[34] Codenamed "Isaiah", the 64-bit architecture was
   unveiled on January 24, 2008,^[35] and launched on May 29 under the VIA
   Nano brand name.^[36]

   The processor supports a number of VIA-specific x86 extensions designed to
   boost efficiency in low-power appliances. It is expected that the Isaiah
   architecture will be twice as fast in integer performance and four times
   as fast in floating-point performance as the previous-generation VIA
   Esther at an equivalent clock speed. Power consumption is also expected to
   be on par with the previous-generation VIA CPUs, with thermal design power
   ranging from 5 W to 25 W.^[37] Being a completely new design, the Isaiah
   architecture was built with support for features like the x86-64
   instruction set and x86 virtualization which were unavailable on its
   predecessors, the VIA C7 line, while retaining their encryption
   extensions.

Microarchitecture levelsEdit

   In 2020, through a collaboration between AMD, Intel, Red Hat, and SUSE,
   three microarchitecture levels on top of the x86-64 baseline were defined:
   x86-64-v2, x86-64-v3, and x86-64-v4.^[38]^[39] These levels define
   specific features that can be targeted by programmers to provide
   compile-time optimizations. The features exposed by each level are as
   follows:^[40]

                          CPU microarchitecture levels
   Level                               CPU features Example instruction 
                                       CMOV         cmov                
                                       CX8          cmpxchg8b           
                                       FPU          fld                 
   x86-64                              FXSR         fxsave              
   (baseline: all x86-64 CPUs)         MMX          emms                
                                       OSFXSR       fxsave              
                                       SCE          syscall             
                                       SSE          cvtss2si            
                                       SSE2         cvtpi2pd            
   x86-64-v2                           CMPXCHG16B   cmpxchg16b          
   (circa 2009: Nehalem and Jaguar)    
                                       LAHF-SAHF    lahf                
   Also:                               POPCNT       popcnt              
                                       SSE3         addsubpd            
     * QEMU Emulation                  SSE4_1       blendpd             
     * Atom Silvermont (2013)          SSE4_2       pcmpestri           
     * VIA Nano and Eden "C" (2015)    SSSE3        phaddd              
                                       AVX          vzeroall            
   x86-64-v3                           AVX2         vpermd              
   (circa 2015: Haswell and Excavator) BMI1         andn                
                                       BMI2         bzhi                
   Also:                               F16C         vcvtph2ps           
                                       FMA          vfmadd132pd         
     * Atom Gracemont (2021)           LZCNT        lzcnt               
                                       MOVBE        movbe               
                                       OSXSAVE      xgetbv              
                                       AVX512F      kmovw               
   x86-64-v4                           AVX512BW     vdbpsadbw           
   (AVX-512's general-purpose subset)  AVX512CD     vplzcntd            
                                       AVX512DQ     vpmullq             
                                       AVX512VL     n/a                 

   All levels include features found in the previous levels. Instruction set
   extensions not concerned with general-purpose computation, including
   AES-NI and RDRAND, are excluded from the level requirements.

Differences between AMD64 and Intel 64Edit

   Although nearly identical, there are some differences between the two
   instruction sets in the semantics of a few seldom used machine
   instructions (or situations), which are mainly used for system
   programming.^[41] Compilers generally produce executables (i.e. machine
   code) that avoid any differences, at least for ordinary application
   programs. This is therefore of interest mainly to developers of compilers,
   operating systems and similar, which must deal with individual and special
   system instructions.

  Recent implementationsEdit

     * Intel 64's BSF and BSR instructions act differently than AMD64's when
       the source is zero and the operand size is 32 bits. The processor sets
       the zero flag and leaves the upper 32 bits of the destination
       undefined^[citation needed]. Note that Intel documents that the
       destination register has an undefined value in this case, but in
       practice in silicon implements the same behaviour as AMD (destination
       unmodified). The separate claim about maybe not preserving bits in the
       upper 32 hasn't been verified, but has only been ruled out for Core 2
       and Skylake,^[42] not all Intel microarchitectures like 64-bit Pentium
       4 or low-power Atom.
     * AMD64 requires a different microcode update format and control MSRs
       (model-specific registers) while Intel 64 implements microcode update
       unchanged from their 32-bit only processors.
     * Intel 64 lacks some MSRs that are considered architectural in AMD64.
       These include SYSCFG, TOP_MEM, and TOP_MEM2.
     * Intel 64 allows SYSCALL/SYSRET only in 64-bit mode (not in
       compatibility mode),^[43] and allows SYSENTER/SYSEXIT in both
       modes.^[44] AMD64 lacks SYSENTER/SYSEXIT in both sub-modes of long
       mode.^[11]^: 33 
     * In 64-bit mode, near branches with the 66H (operand size override)
       prefix behave differently. Intel 64 ignores this prefix: the
       instruction has 32-bit sign extended offset, and instruction pointer
       is not truncated. AMD64 uses 16-bit offset field in the instruction,
       and clears the top 48 bits of instruction pointer.
     * AMD processors raise a floating-point Invalid Exception when
       performing an FLD or FSTP of an 80-bit signalling NaN, while Intel
       processors do not.
     * Intel 64 lacks the ability to save and restore a reduced (and thus
       faster) version of the floating-point state (involving the FXSAVE and
       FXRSTOR instructions).^[clarification needed]
     * AMD processors ever since Opteron Rev. E and Athlon 64 Rev. D have
       reintroduced limited support for segmentation, via the Long Mode
       Segment Limit Enable (LMSLE) bit, to ease virtualization of 64-bit
       guests.^[45]^[46]
     * When returning to a non-canonical address using SYSRET, AMD64
       processors execute the general protection fault handler in privilege
       level 3,^[47] while on Intel 64 processors it is executed in privilege
       level 0.^[48]

  Older implementationsEdit

     * Early AMD64 processors (typically on Socket 939 and 940) lacked the
       CMPXCHG16B instruction, which is an extension of the CMPXCHG8B
       instruction present on most post-80486 processors. Similar to
       CMPXCHG8B, CMPXCHG16B allows for atomic operations on octa-words
       (128-bit values). This is useful for parallel algorithms that use
       compare and swap on data larger than the size of a pointer, common in
       lock-free and wait-free algorithms. Without CMPXCHG16B one must use
       workarounds, such as a critical section or alternative lock-free
       approaches.^[49] Its absence also prevents 64-bit Windows prior to
       Windows 8.1 from having a user-mode address space larger than
       8 TiB.^[50] The 64-bit version of Windows 8.1 requires the
       instruction.^[51]
     * Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in
       64-bit mode. AMD introduced these instructions (also in 64-bit mode)
       with their Athlon 64, Opteron and Turion 64 revision D processors in
       March 2005^[52]^[53]^[54] while Intel introduced the instructions with
       the Pentium 4 G1 stepping in December 2005. The 64-bit version of
       Windows 8.1 requires this feature.^[51]
     * Early Intel CPUs with Intel 64 also lack the NX bit of the AMD64
       architecture. This feature is required by all versions of Windows 8.x.
     * Early Intel 64 implementations (Prescott and Cedar Mill) only allowed
       access to 64 GiB of physical memory while original AMD64
       implementations allowed access to 1 TiB of physical memory.
       Recent^[when?] AMD64 implementations provide 256 TiB of physical
       address space (and AMD plans an expansion to 4 PiB),^[citation needed]
       while some Intel 64 implementations could address up to 64 TiB.^[55]
       Physical memory capacities of this size are appropriate for
       large-scale applications (such as large databases), and
       high-performance computing (centrally oriented applications and
       scientific computing).

AdoptionEdit

   [IMG] 
   Enlarge
   An area chart showing the representation of different families of
   microprocessors in the TOP500 supercomputer ranking list, from 1993 to
   2019.^[56]

   In supercomputers tracked by TOP500, the appearance of 64-bit extensions
   for the x86 architecture enabled 64-bit x86 processors by AMD and Intel to
   replace most RISC processor architectures previously used in such systems
   (including PA-RISC, SPARC, Alpha and others), as well as 32-bit x86, even
   though Intel itself initially tried unsuccessfully to replace x86 with a
   new incompatible 64-bit architecture in the Itanium processor.

   As of 2020, a Fujitsu A64FX-based supercomputer called Fugaku is number
   one. The first ARM-based supercomputer appeared on the list in 2018^[57]
   and, in recent years, non-CPU architecture co-processors (GPGPU) have also
   played a big role in performance. Intel's Xeon Phi "Knights Corner"
   coprocessors, which implement a subset of x86-64 with some vector
   extensions,^[58] are also used, along with x86-64 processors, in the
   Tianhe-2 supercomputer.^[59]

Operating system compatibility and characteristicsEdit

   The following operating systems and releases support the x86-64
   architecture in long mode.

  BSDEdit

    DragonFly BSDEdit

   Preliminary infrastructure work was started in February 2004 for a x86-64
   port.^[60] This development later stalled. Development started again
   during July 2007^[61] and continued during Google Summer of Code 2008 and
   SoC 2009.^[62]^[63] The first official release to contain x86-64 support
   was version 2.4.^[64]

    FreeBSDEdit

   FreeBSD first added x86-64 support under the name "amd64" as an
   experimental architecture in 5.1-RELEASE in June 2003. It was included as
   a standard distribution architecture as of 5.2-RELEASE in January 2004.
   Since then, FreeBSD has designated it as a Tier 1 platform. The
   6.0-RELEASE version cleaned up some quirks with running x86 executables
   under amd64, and most drivers work just as they do on the x86
   architecture. Work is currently being done to integrate more fully the x86
   application binary interface (ABI), in the same manner as the Linux 32-bit
   ABI compatibility currently works.

    NetBSDEdit

   x86-64 architecture support was first committed to the NetBSD source tree
   on June 19, 2001. As of NetBSD 2.0, released on December 9, 2004,
   NetBSD/amd64 is a fully integrated and supported port. 32-bit code is
   still supported in 64-bit mode, with a netbsd-32 kernel compatibility
   layer for 32-bit syscalls. The NX bit is used to provide non-executable
   stack and heap with per-page granularity (segment granularity being used
   on 32-bit x86).

    OpenBSDEdit

   OpenBSD has supported AMD64 since OpenBSD 3.5, released on May 1, 2004.
   Complete in-tree implementation of AMD64 support was achieved prior to the
   hardware's initial release because AMD had loaned several machines for the
   project's hackathon that year. OpenBSD developers have taken to the
   platform because of its support for the NX bit, which allowed for an easy
   implementation of the W^X feature.

   The code for the AMD64 port of OpenBSD also runs on Intel 64 processors
   which contains cloned use of the AMD64 extensions, but since Intel left
   out the page table NX bit in early Intel 64 processors, there is no W^X
   capability on those Intel CPUs; later Intel 64 processors added the NX bit
   under the name "XD bit". Symmetric multiprocessing (SMP) works on
   OpenBSD's AMD64 port, starting with release 3.6 on November 1, 2004.

  DOSEdit

   It is possible to enter long mode under DOS without a DOS extender,^[65]
   but the user must return to real mode in order to call BIOS or DOS
   interrupts.

   It may also be possible to enter long mode with a DOS extender similar to
   DOS/4GW, but more complex since x86-64 lacks virtual 8086 mode. DOS itself
   is not aware of that, and no benefits should be expected unless running
   DOS in an emulation with an adequate virtualization driver backend, for
   example: the mass storage interface.

  LinuxEdit

   Link: mw-deduplicated-inline-style
   See also: Comparison of Linux distributions § Instruction set architecture
   support

   Linux was the first operating system kernel to run the x86-64 architecture
   in long mode, starting with the 2.4 version in 2001 (preceding the
   hardware's availability).^[66]^[67] Linux also provides backward
   compatibility for running 32-bit executables. This permits programs to be
   recompiled into long mode while retaining the use of 32-bit programs.
   Several Linux distributions currently ship with x86-64-native kernels and
   userlands. Some, such as Arch Linux,^[68] SUSE, Mandriva, and Debian allow
   users to install a set of 32-bit components and libraries when installing
   off a 64-bit DVD, thus allowing most existing 32-bit applications to run
   alongside the 64-bit OS. Other distributions, such as Fedora, Slackware
   and Ubuntu, are available in one version compiled for a 32-bit
   architecture and another compiled for a 64-bit architecture. Fedora and
   Red Hat Enterprise Linux allow concurrent installation of all userland
   components in both 32 and 64-bit versions on a 64-bit system.

   x32 ABI (Application Binary Interface), introduced in Linux 3.4, allows
   programs compiled for the x32 ABI to run in the 64-bit mode of x86-64
   while only using 32-bit pointers and data fields.^[69]^[70]^[71] Though
   this limits the program to a virtual address space of 4 GiB it also
   decreases the memory footprint of the program and in some cases can allow
   it to run faster.^[69]^[70]^[71]

   64-bit Linux allows up to 128 TiB of virtual address space for individual
   processes, and can address approximately 64 TiB of physical memory,
   subject to processor and system limitations.^[72]

  macOSEdit

   Mac OS X 10.4.7 and higher versions of Mac OS X 10.4 run 64-bit
   command-line tools using the POSIX and math libraries on 64-bit
   Intel-based machines, just as all versions of Mac OS X 10.4 and 10.5 run
   them on 64-bit PowerPC machines. No other libraries or frameworks work
   with 64-bit applications in Mac OS X 10.4.^[73] The kernel, and all kernel
   extensions, are 32-bit only.

   Mac OS X 10.5 supports 64-bit GUI applications using Cocoa, Quartz,
   OpenGL, and X11 on 64-bit Intel-based machines, as well as on 64-bit
   PowerPC machines.^[74] All non-GUI libraries and frameworks also support
   64-bit applications on those platforms. The kernel, and all kernel
   extensions, are 32-bit only.

   Mac OS X 10.6 is the first version of macOS that supports a 64-bit kernel.
   However, not all 64-bit computers can run the 64-bit kernel, and not all
   64-bit computers that can run the 64-bit kernel will do so by
   default.^[75] The 64-bit kernel, like the 32-bit kernel, supports 32-bit
   applications; both kernels also support 64-bit applications. 32-bit
   applications have a virtual address space limit of 4 GiB under either
   kernel.^[76]^[77] The 64-bit kernel does not support 32-bit kernel
   extensions, and the 32-bit kernel does not support 64-bit kernel
   extensions.

   OS X 10.8 includes only the 64-bit kernel, but continues to support 32-bit
   applications; it does not support 32-bit kernel extensions, however.

   macOS 10.15 includes only the 64-bit kernel and no longer supports 32-bit
   applications. This removal of support has presented a problem for WineHQ
   (and the commercial version CrossOver), as it needs to still be able to
   run 32-bit Windows applications. The solution, termed wine32on64, was to
   add thunks that bring the CPU in and out of 32-bit compatibility mode in
   the nominally 64-bit application.^[78]^[79]

   macOS uses the universal binary format to package 32- and 64-bit versions
   of application and library code into a single file; the most appropriate
   version is automatically selected at load time. In Mac OS X 10.6, the
   universal binary format is also used for the kernel and for those kernel
   extensions that support both 32-bit and 64-bit kernels.

  SolarisEdit

   Link: mw-deduplicated-inline-style
   See also: illumos

   Solaris 10 and later releases support the x86-64 architecture.

   For Solaris 10, just as with the SPARC architecture, there is only one
   operating system image, which contains a 32-bit kernel and a 64-bit
   kernel; this is labeled as the "x64/x86" DVD-ROM image. The default
   behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or
   new 32-bit executables to be run. A 32-bit kernel can also be manually
   selected, in which case only 32-bit executables will run. The isainfo
   command can be used to determine if a system is running a 64-bit kernel.

   For Solaris 11, only the 64-bit kernel is provided. However, the 64-bit
   kernel supports both 32- and 64-bit executables, libraries, and system
   calls.

  WindowsEdit

   x64 editions of Microsoft Windows client and server—Windows XP
   Professional x64 Edition and Windows Server 2003 x64 Edition—were released
   in March 2005.^[80] Internally they are actually the same build
   (5.2.3790.1830 SP1),^[81]^[82] as they share the same source base and
   operating system binaries, so even system updates are released in unified
   packages, much in the manner as Windows 2000 Professional and Server
   editions for x86. Windows Vista, which also has many different editions,
   was released in January 2007. Windows 7 was released in July 2009. Windows
   Server 2008 R2 was sold in only x64 and Itanium editions; later versions
   of Windows Server only offer an x64 edition.

   Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012
   R2 offer the following:

     * 8 TiB of virtual address space per process, accessible from both user
       mode and kernel mode, referred to as the user mode address space. An
       x64 program can use all of this, subject to backing store limits on
       the system, and provided it is linked with the "large address aware"
       option.^[83] This is a 4096-fold increase over the default 2 GiB
       user-mode virtual address space offered by 32-bit Windows.^[84]^[85]
     * 8 TiB of kernel mode virtual address space for the operating
       system.^[84] As with the user mode address space, this is a 4096-fold
       increase over 32-bit Windows versions. The increased space primarily
       benefits the file system cache and kernel mode "heaps" (non-paged pool
       and paged pool). Windows only uses a total of 16 TiB out of the
       256 TiB implemented by the processors because early AMD64 processors
       lacked a CMPXCHG16B instruction.^[86]

   Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel
   mode virtual address spaces have been extended to 128 TiB.^[22] These
   versions of Windows will not install on processors that lack the
   CMPXCHG16B instruction.

   The following additional characteristics apply to all x64 versions of
   Windows:

     * Ability to run existing 32-bit applications (.exe programs) and
       dynamic link libraries (.dlls) using WoW64 if WoW64 is supported on
       that version. Furthermore, a 32-bit program, if it was linked with the
       "large address aware" option,^[83] can use up to 4 GiB of virtual
       address space in 64-bit Windows, instead of the default 2 GiB
       (optional 3 GiB with /3GB boot option and "large address aware" link
       option) offered by 32-bit Windows.^[87] Unlike the use of the /3GB
       boot option on x86, this does not reduce the kernel mode virtual
       address space available to the operating system. 32-bit applications
       can, therefore, benefit from running on x64 Windows even if they are
       not recompiled for x86-64.
     * Both 32- and 64-bit applications, if not linked with "large address
       aware," are limited to 2 GiB of virtual address space.
     * Ability to use up to 128 GiB (Windows XP/Vista), 192 GiB (Windows 7),
       512 GiB (Windows 8), 1 TiB (Windows Server 2003), 2 TiB (Windows
       Server 2008/Windows 10), 4 TiB (Windows Server 2012), or 24 TiB
       (Windows Server 2016/2019) of physical random access memory
       (RAM).^[88]
     * LLP64 data model: "int" and "long" types are 32 bits wide, long long
       is 64 bits, while pointers and types derived from pointers are 64 bits
       wide.
     * Kernel mode device drivers must be 64-bit versions; there is no way to
       run 32-bit kernel mode executables within the 64-bit operating system.
       User mode device drivers can be either 32-bit or 64-bit.
     * 16-bit Windows (Win16) and DOS applications will not run on x86-64
       versions of Windows due to the removal of the virtual DOS machine
       subsystem (NTVDM) which relied upon the ability to use virtual 8086
       mode. Virtual 8086 mode cannot be entered while running in long mode.
     * Full implementation of the NX (No Execute) page protection feature.
       This is also implemented on recent 32-bit versions of Windows when
       they are started in PAE mode.
     * Instead of FS segment descriptor on x86 versions of the Windows NT
       family, GS segment descriptor is used to point to two operating system
       defined structures: Thread Information Block (NT_TIB) in user mode and
       Processor Control Region (KPCR) in kernel mode. Thus, for example, in
       user mode GS:0 is the address of the first member of the Thread
       Information Block. Maintaining this convention made the x86-64 port
       easier, but required AMD to retain the function of the FS and GS
       segments in long mode – even though segmented addressing per se is not
       really used by any modern operating system.^[84]
     * Early reports claimed that the operating system scheduler would not
       save and restore the x87 FPU machine state across thread context
       switches. Observed behavior shows that this is not the case: the x87
       state is saved and restored, except for kernel mode-only threads (a
       limitation that exists in the 32-bit version as well). The most recent
       documentation available from Microsoft states that the x87/MMX/3DNow!
       instructions may be used in long mode, but that they are deprecated
       and may cause compatibility problems in the future.^[87]
     * Some components like Jet Database Engine and Data Access Objects will
       not be ported to 64-bit architectures such as x86-64 and
       IA-64.^[89]^[90]^[91]
     * Microsoft Visual Studio can compile native applications to target
       either the x86-64 architecture, which can run only on 64-bit Microsoft
       Windows, or the IA-32 architecture, which can run as a 32-bit
       application on 32-bit Microsoft Windows or 64-bit Microsoft Windows in
       WoW64 emulation mode. Managed applications can be compiled either in
       IA-32, x86-64 or AnyCPU modes. Software created in the first two modes
       behave like their IA-32 or x86-64 native code counterparts
       respectively; When using the AnyCPU mode, however, applications in
       32-bit versions of Microsoft Windows run as 32-bit applications, while
       they run as a 64-bit application in 64-bit editions of Microsoft
       Windows.

Video game consolesEdit

   Both PlayStation 4 and Xbox One and their variants incorporate AMD x86-64
   processors, based on the Jaguar microarchitecture.^[92]^[93] Firmware and
   games are written in x86-64 code; no legacy x86 code is involved.

   Their next generations, the PlayStation 5 and the Xbox Series X and Series
   S respectively, also incorporate AMD x86-64 processors, based on the Zen 2
   microarchitecture.^[94]^[95]

Industry naming conventionsEdit

   Since AMD64 and Intel 64 are substantially similar, many software and
   hardware products use one vendor-neutral term to indicate their
   compatibility with both implementations. AMD's original designation for
   this processor architecture, "x86-64", is still sometimes used for this
   purpose,^[2] as is the variant "x86_64".^[3]^[4] Other companies, such as
   Microsoft^[6] and Sun Microsystems/Oracle Corporation,^[5] use the
   contraction "x64" in marketing material.

   The term IA-64 refers to the Itanium processor, and should not be confused
   with x86-64, as it is a completely different instruction set.

   Many operating systems and products, especially those that introduced
   x86-64 support prior to Intel's entry into the market, use the term
   "AMD64" or "amd64" to refer to both AMD64 and Intel 64.

     * amd64
          * Most BSD systems such as FreeBSD, MidnightBSD, NetBSD and OpenBSD
            refer to both AMD64 and Intel 64 under the architecture name
            "amd64".
          * Some Linux distributions such as Debian, Ubuntu, Gentoo Linux
            refer to both AMD64 and Intel 64 under the architecture name
            "amd64".
          * Microsoft Windows's x64 versions use the AMD64 moniker internally
            to designate various components which use or are compatible with
            this architecture. For example, the environment variable
            PROCESSOR_ARCHITECTURE is assigned the value "AMD64" as opposed
            to "x86" in 32-bit versions, and the system directory on a
            Windows x64 Edition installation CD-ROM is named "AMD64", in
            contrast to "i386" in 32-bit versions.^[96]
          * Sun's Solaris's isalist command identifies both AMD64- and Intel
            64-based systems as "amd64".
          * Java Development Kit (JDK): the name "amd64" is used in directory
            names containing x86-64 files.
     * x86_64
          * The Linux kernel^[97] and the GNU Compiler Collection refers to
            64-bit architecture as "x86_64".
          * Some Linux distributions, such as Fedora, openSUSE, Arch Linux,
            Gentoo Linux refer to this 64-bit architecture as "x86_64".
          * Apple macOS refers to 64-bit architecture as "x86-64" or
            "x86_64", as seen in the Terminal command arch^[3] and in their
            developer documentation.^[2]^[4]
          * Breaking with most other BSD systems, DragonFly BSD refers to
            64-bit architecture as "x86_64".
          * Haiku refers to 64-bit architecture as "x86_64".

LicensingEdit

   x86-64/AMD64 was solely developed by AMD. AMD holds patents on techniques
   used in AMD64;^[98]^[99]^[100] those patents must be licensed from AMD in
   order to implement AMD64. Intel entered into a cross-licensing agreement
   with AMD, licensing to AMD their patents on existing x86 techniques, and
   licensing from AMD their patents on techniques used in x86-64.^[101] In
   2009, AMD and Intel settled several lawsuits and cross-licensing
   disagreements, extending their cross-licensing
   agreements.^[102]^[103]^[104]

See alsoEdit

     * AMD Generic Encapsulated Software Architecture (AGESA)
     * IA-32
     * x86

NotesEdit

   Link: mw-deduplicated-inline-style
    1. ^ Various names are used for the instruction set. Prior to the launch,
       x86-64 and x86_64 were used, while upon the release AMD named it
       AMD64.^[1] Intel initially used the names IA-32e and EM64T before
       finally settling on "Intel 64" for its implementation. Some in the
       industry, including Apple,^[2]^[3]^[4] use x86-64 and x86_64, while
       others, notably Sun Microsystems^[5] (now Oracle Corporation) and
       Microsoft,^[6] use x64. The BSD family of OSs and several Linux
       distributions^[7]^[8] use AMD64, as does Microsoft Windows
       internally.^[9]^[10]
    2. ^ In practice, 64-bit operating systems generally do not support
       16-bit applications, although modern versions of Microsoft Windows
       contain a limited workaround that effectively supports 16-bit
       InstallShield and Microsoft ACME installers by silently substituting
       them with 32-bit code.^[12]

ReferencesEdit

   Link: mw-deduplicated-inline-style
    1. ^ "Debian AMD64 FAQ". Debian Wiki. Archived from the original on
       September 26, 2019. Retrieved May 3, 2012.
    2. ^ ^a ^b ^c
       Link: mw-deduplicated-inline-style
       "x86-64 Code Model". Apple. Archived from the original on June 2,
       2012. Retrieved November 23, 2012.
    3. ^ ^a ^b ^c arch(1) – Darwin and macOS General Commands Manual
    4. ^ ^a ^b ^c
       Link: mw-deduplicated-inline-style
       Kevin Van Vechten (August 9, 2006). "re: Intel XNU bug report".
       Darwin-dev mailing list. Apple Computer. Archived from the original on
       February 1, 2020. Retrieved October 5, 2006. The kernel and developer
       tools have standardized on "x86_64" for the name of the Mach-O
       architecture
    5. ^ ^a ^b
       Link: mw-deduplicated-inline-style
       "Solaris 10 on AMD Opteron". Oracle. Archived from the original on
       July 25, 2017. Retrieved December 9, 2010.
    6. ^ ^a ^b
       Link: mw-deduplicated-inline-style
       "Microsoft 64-Bit Computing". Microsoft. Archived from the original on
       December 12, 2010. Retrieved December 9, 2010.
    7. ^
       Link: mw-deduplicated-inline-style
       "AMD64 Port". Debian. Archived from the original on September 26,
       2019. Retrieved November 23, 2012.
    8. ^
       Link: mw-deduplicated-inline-style
       "Gentoo/AMD64 Project". Gentoo Project. Archived from the original on
       June 3, 2013. Retrieved May 27, 2013.
    9. ^
       Link: mw-deduplicated-inline-style
       "WOW64 Implementation Details". Archived from the original on April
       13, 2018. Retrieved January 24, 2016.
   10. ^
       Link: mw-deduplicated-inline-style
       "ProcessorArchitecture Class". Archived from the original on June 3,
       2017. Retrieved January 24, 2016.
   11. ^ ^a ^b ^c ^d ^e ^f ^g ^h ^i ^j ^k ^l ^m ^n ^o ^p ^q ^r ^s ^t ^u
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External linksEdit

     * AMD Developer Guides, Manuals & ISA Documents
     * x86-64: Extending the x86 architecture to 64-bits – technical talk by
       the architect of AMD64 (video archive), and second talk by the same
       speaker (video archive)
     * AMD's "Enhanced Virus Protection"
     * Intel tweaks EM64T for full AMD64 compatibility
     * Analyst: Intel Reverse-Engineered AMD64
     * Early report of differences between Intel IA32e and AMD64
     * Porting to 64-bit GNU/Linux Systems, by Andreas Jaeger from GCC Summit
       2003. An excellent paper explaining almost all practical aspects for a
       transition from 32-bit to 64-bit.
     * Intel 64 Architecture
     * Intel Software Network: "64 bits"
     * TurboIRC.COM tutorials, including examples of how to of enter
       protected and long mode the raw way from DOS
     * Seven Steps of Migrating a Program to a 64-bit System
     * Memory Limits for Windows Releases
   Retrieved from
   "https://en.wikipedia.org/w/index.php?title=X86-64&oldid=1081751887"
   Last edited on 9 April 2022, at 12:50
   Wikipedia
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